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| m68hc08 microcontrollers freescale.com mc68hc908jl8 mc68hc908jk8 mc68hc908kl8 mc68hc08jl8 MC68HC08JK8 data sheet mc68hc908jl8 rev. 3.1 3/2005
mc68hc908jl8/jk8 ? mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 3 freescale? and the freescale logo are trade marks of freescale semiconductor, inc. this product incorporates superflash? technology licensed from sst. ? freescale semiconductor, inc., 200 5 . all rights reserved. mc68hc908jl8 mc68hc908jk8 mc68hc908kl8 mc68hc08jl8 MC68HC08JK8 data sheet to provide the most up-to-date information, the revisi on of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://www.freescale.com the following revision history table summarizes changes contained in this document. for your convenience, the page number designators have been linked to the appropriate location. mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 4 freescale semiconductor revision history date revision level description page number(s) mar 2005 3.1 added irq timing to table 17-5 . control timing (5v) and table 17-8 . control timing (3v) 188 , 190 nov 2004 3 chapter 9 serial communications interface (sci) ? corrected sci module clock source from oscclk to bus clock throughout. 121?206 figure 13-2 . keyboard interrupt block diagram ? removed incorrect schmitt trigger in block diagram. 168 14.7.2 stop mode ? stop_iclkdis bit does not affect stop mode conditions for cop. replaced section with new text. 176 added appendix a mc68hc08jl8 ? rom parts. 201 added appendix b mc68hc908kl8 . 207 nov 2002 2 first general release. ? mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 5 list of chapters chapter 1 general descr iption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 chapter 2 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 chapter 3 configuration and mask option register s (config & mor) . . . . . . . . . . . . . . 41 chapter 4 central processor unit (cpu). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 chapter 5 system integr ation module (sim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 chapter 6 oscillator (osc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 chapter 7 monitor rom (mon) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 chapter 8 timer interface module (tim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 chapter 9 serial communications interf ace (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 chapter 10 analog-to-digital converter (adc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 chapter 11 input/output (i/o) port s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 chapter 12 external in terrupt (irq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 chapter 13 keyboard interrupt m odule (kbi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 chapter 14 computer operati ng properly (cop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 chapter 15 low voltage inhi bit (lvi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 chapter 16 break module (break) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 chapter 17 electrical spec ifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 chapter 18 mechanical specificati ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 chapter 19 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 appendix a mc68hc08jl8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 appendix b mc68hc908kl8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 list of chapters mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 6 freescale semiconductor mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 7 table of contents chapter 1 general description 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.3 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.4 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.5 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 chapter 2 memory 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.2 i/o section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3 monitor rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4 random-access memory (ram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.5 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.7 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.8 flash page erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.9 flash mass erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.10 flash program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.11 flash block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.12 flash block protect register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 chapter 3 configuration and mask option register s (config & mor) 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.3 configuration register 1 (config1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.4 configuration register 2 (config2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.5 mask option register (mor). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 chapter 4 central processor unit (cpu) 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.3 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.3.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.3.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.3.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table of contents mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 8 freescale semiconductor 4.3.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.3.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.4 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.6 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.7 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.8 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 chapter 5 system integrati on module (sim) 5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.2 sim bus clock control and generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.2.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.2.2 clock start-up from por or lvi reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.2.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.3 reset and system initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.3.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.3.2 active resets from internal sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.3.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 5.3.2.2 computer operating properly (cop) reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.3.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.3.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.3.2.5 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.4 sim counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.4.1 sim counter during power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.4.2 sim counter during stop mode recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.4.3 sim counter and reset states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 5.5 exception control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.5.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.5.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.5.1.2 swi instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.5.2 interrupt status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.5.2.1 interrupt status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.5.2.2 interrupt status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.5.2.3 interrupt status register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.5.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.5.4 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.5.5 status flag protection in break mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5.7 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.7.1 break status register (bsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.7.2 reset status register (rsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.7.3 break flag control register (bfcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 9 chapter 6 oscillator (osc) 6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.2 oscillator selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.2.1 xtal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.2.2 rc oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.3 internal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.4.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.4.2 crystal amplifier output pin (osc2/rcclk/pta6/kbi6 ) . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.4.3 oscillator enable signal (simoscen) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.4.4 xtal oscillator clock (xtalclk). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.4.5 rc oscillator clock (rcclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.4.6 oscillator out 2 (2oscout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6.4.7 oscillator out (oscout). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.4.8 internal oscillator clock (iclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.6 oscillator during break mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 chapter 7 monitor rom (mon) 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 7.3.1 entering monitor mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.3.2 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.3.3 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.3.4 echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.3.5 break signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.3.6 commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.4 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.5 rom-resident routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 7.5.1 prgrnge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.5.2 erarnge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.5.3 ldrnge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.5.4 mon_prgrnge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.5.5 mon_erarnge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 7.5.6 mon_ldrnge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.5.7 ee_write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 7.5.8 ee_read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table of contents mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 10 freescale semiconductor chapter 8 timer interface module (tim) 8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.3 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8.4.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 8.4.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 8.4.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 8.4.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 8.4.3.2 buffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 9 8.4.4 pulse width modulation (pwm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 8.4.4.1 unbuffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.4.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.4.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 8.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 8.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 8.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 8.7 tim during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.8 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.8.1 tim clock pin (adc12/t2clk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.8.2 tim channel i/o pins (ptd4/t1ch0, ptd5/t1ch1, pte0/t2ch0, pte1/t2ch1) . . . . . 113 8.9 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.9.1 tim status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 8.9.2 tim counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8.9.3 tim counter modulo registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 8.9.4 tim channel status and control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8.9.5 tim channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 chapter 9 serial communications interface (sci) 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 9.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 9.3 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 9.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 9.4.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 9.4.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9.4.2.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9.4.2.2 character transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 9.4.2.3 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 9.4.2.4 idle characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 9.4.2.5 inversion of transmitted output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 9.4.2.6 transmitter interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 9.4.3 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 9.4.3.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 11 9.4.3.2 character reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 9.4.3.3 data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 9.4.3.4 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 9.4.3.5 baud rate tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 9.4.3.6 receiver wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 9.4.3.7 receiver interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 9.4.3.8 error interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 9.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9.6 sci during break module interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 33 9.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9.7.1 txd (transmit data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9.7.2 rxd (receive data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9.8 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 9.8.1 sci control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 9.8.2 sci control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 9.8.3 sci control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 9.8.4 sci status register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 9.8.5 sci status register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 9.8.6 sci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 9.8.7 sci baud rate register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 chapter 10 analog-to-digital converter (adc) 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 10.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 10.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 10.3.1 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 10.3.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 10.3.3 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 10.3.4 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 10.3.5 accuracy and precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 10.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 10.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 10.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 10.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 10.6 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 10.6.1 adc voltage in (adcvin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 10.7 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 10.7.1 adc status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 10.7.2 adc data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 10.7.3 adc input clock register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 table of contents mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 12 freescale semiconductor chapter 11 input/output (i/o) ports 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 11.2 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 11.2.1 port a data register (pta) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 11.2.2 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 11.2.3 port a input pull-up enable register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 11.3 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 11.3.1 port b data register (ptb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 11.3.2 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 11.4 port d. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 11.4.1 port d data register (ptd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 11.4.2 data direction register d (ddrd). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 11.4.3 port d control register (pdcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 0 11.5 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 11.5.1 port e data register (pte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 11.5.2 data direction register e (ddre) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 chapter 12 external interrupt (irq) 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 12.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 12.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 12.3.1 irq pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 12.4 irq module during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 12.5 irq status and control register (intscr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 chapter 13 keyboard interrupt module (kbi) 13.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 13.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 13.3 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 13.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 13.4.1 keyboard initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 13.5 keyboard interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 13.5.1 keyboard status and control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 13.5.2 keyboard interrupt enable register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 13.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 13.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 13.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 13.7 keyboard module during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 chapter 14 computer operatin g properly (cop) 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 14.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 13 14.3 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 14.3.1 iclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 14.3.2 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 14.3.3 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 14.3.4 internal reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 14.3.5 reset vector fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 14.3.6 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 14.3.7 coprs (cop rate select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 75 14.4 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 14.5 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 14.6 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 14.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 14.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 14.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 14.8 cop module during break mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 chapter 15 low voltage inhibit (lvi) 15.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 15.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 15.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 15.4 lvi control register (config2/config1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 15.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 15.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 15.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 chapter 16 break module (break) 16.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 16.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 16.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 16.3.1 flag protection during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 16.3.2 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 16.3.3 tim during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 16.3.4 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 16.4 break module registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 16.4.1 break status and control register (brkscr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 16.4.2 break address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 16.4.3 break status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 16.4.4 break flag control register (bfcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 16.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 16.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 16.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 table of contents mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 14 freescale semiconductor chapter 17 electrical specifications 17.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 17.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 17.3 functional operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 17.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 17.5 5v dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 17.6 5v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 17.7 5v oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 17.8 3v dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 17.9 3v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 17.10 3v oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 17.11 typical supply currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 17.12 timer interface module characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 17.13 adc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 17.14 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 chapter 18 mechanical specifications 18.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 18.2 20-pin plastic dual in-line package (pdip) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 18.3 20-pin small outline integrated circuit package (soic). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 18.4 28-pin plastic dual in-line package (pdip) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 18.5 28-pin small outline integrated circuit package (soic). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 18.6 32-pin shrink dual in-line package (s dip) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 18.7 32-pin low-profile quad flat pack (lqf p) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 chapter 19 ordering information 19.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 19.2 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 appendix a mc68hc08jl8 a.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 a.2 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 a.3 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 a.4 reserved registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 a.5 mask option register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 a.6 monitor rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 a.7 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 a.7.1 dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 a.8 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 a.9 mc68hc08jl8 order numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 15 appendix b mc68hc908kl8 b.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 b.2 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 b.3 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 b.4 reserved registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 b.5 reserved vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 b.6 mc68hc908kl8 order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 table of contents mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 16 freescale semiconductor mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 17 chapter 1 general description 1.1 introduction the mc68hc908jl8 is a member of the low-co st, high-performance m68hc08 family of 8-bit microcontroller units (mcus). all mcus in the fa mily use the enhanced m68hc 08 central processor unit (cpu08) and are available with a variety of mo dules, memory sizes and types, and package types. 1.2 features features of the mc68hc908jl8 include the following: high-performance m68hc08 architecture fully upward-compatible object code wi th m6805, m146805, and m68hc05 families low-power design; fully static with stop and wait modes maximum internal bus frequency: ? 8-mhz at 5v operating voltage ? 4-mhz at 3v operating voltage oscillator options: ? crystal or resonator ? rc oscillator 8,192 bytes user program flash memory with security (1) feature 256 bytes of on-chip ram two 16-bit, 2-channel timer interface modules (tim1 and tim2) with selectable input capture, output compare, and pwm capability on each channel; external clock input option on tim2 13-channel, 8-bit analog-to-digital converter (adc) serial communications interface module (sci) 26 general-purpose input/output (i/o) ports: ? 8 keyboard interrupt with internal pull-up table 1-1. summary of devices generic part description pin count mc68hc908jl8 flash part 28 or 32 mc68hc908jk8 flash part 20 mc68hc08jl8 rom part for mc68hc908jl8 28 or 32 MC68HC08JK8 rom part for mc68hc908jk8 20 mc68hc908kl8 adc-less mc68hc908jl8 28 or 32 1. no security feature is absolutely secure . however, motorola?s strategy is to make reading or copying the flash difficult for unauthorized users. general description mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 18 freescale semiconductor ? 11 led drivers (sink) ?2 mcu block diagram mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 19 figure 1-1. mc68hc908jl8 block diagram system integration module arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 64 bytes external interrupt module internal bus * rst * irq power vss 2-channel timer interface module 1 keyboard interrupt module 8-bit analog-to-digital converter module vdd adc reference ddrb portb ptb7/adc7 ptb6/adc6 ptb5/adc5 ptb4/adc4 ptb3/adc3 ptb2/adc2 ptb1/adc1 ptb0/adc0 ddra porta pta6/kbi6** pta5/kbi5** ? pta4/kbi4** ? pta3/kbi3** ? pta2/kbi2** ? pta1/kbi1** ? pta0/kbi0** ? power-on reset module * pin contains integrated pull-up device. ** pin contains programmable pull-up device. ? led direct sink pin. osc1 osc2/rcclk crystal oscillator rc oscillator ddrd portd ptd7/rxd ** ?? ptd6/txd ** ?? ptd5/t1ch1 ptd4/t1ch0 ptd3/adc8 ? ptd2/adc9 ? ptd1/adc10 ptd0/adc11 break module computer operating properly module # pins available on 32-pin packages only. shared pin: osc2/rcclk/pta6/kbi6. pta7/kbi7** ? low-voltage inhibit module serial communications interface module pte ddre pte1/t2ch1 pte0/t2ch0 internal oscillator adc12/t2clk 2-channel timer interface module 2 user flash ? 8,192 bytes user ram ? 256 bytes monitor rom ? 959 bytes user flash vectors ? 36 bytes # ## # ## # ## pins available on 28-pin and 32-pin packages only. ? 25ma open-drain if output pin. general description mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 20 freescale semiconductor 1.4 pin assignments figure 1-2. 32-pin lqfp pin assignment figure 1-3. 32-pin sdip pin assignment 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 24 20 19 18 17 9 23 22 21 irq pta0/kbi0 vss osc1 osc2/rcclk/pta6/kbi6 pta1/kbi1 vdd pta2/kbi2 pta3/kbi3 ptb7/adc7 ptb6/adc6 ptb5/adc5 adc12/t2clk pta7/kbi7 rst pta5/kbi5 ptd4/t1ch0 ptd5/t1ch1 ptd2/adc9 pta4/kbi4 ptd3/adc8 ptb0/adc0 ptb1/adc1 ptd1/adc10 ptb2/adc2 ptb4/adc4 ptd0/adc11 ptb3/adc3 ptd7/rxd ptd6/txd pte0/t2ch0 pte1/t2ch1 1 2 3 4 5 6 7 32 31 30 29 28 27 26 25 24 23 22 12 13 14 21 20 19 8 9 10 11 adc12/t2clk pta7/kbi7 rst pta5/kbi5 ptd4/t1ch0 ptd5/t1ch1 ptd2/adc9 pta4/kbi4 ptd3/adc8 ptb0/adc0 ptb1/adc1 ptd1/adc10 ptb2/adc2 ptb3/adc3 irq pta0/kbi0 vss osc1 osc2/rcclk/pta6/kbi6 pta1/kbi1 vdd pta2/kbi2 pta3/kbi3 ptb7/adc7 ptb6/adc6 ptb5/adc5 ptd7/rxd ptd6/txd 15 16 18 17 ptd0/adc11 ptb4/adc4 pte0/t2ch0 pte1/t2ch1 pin functions mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 21 figure 1-4. 28-pin pdip/soic pin assignment figure 1-5. 20-pin pdip/soic pin assignment 1.5 pin functions description of the pin functions are provided in table 1-2 . 1 2 3 4 5 6 7 28 27 26 25 24 23 22 21 20 19 18 12 13 14 17 16 15 8 9 10 11 rst pta5/kbi5 ptd4/t1ch0 ptd5/t1ch1 ptd2/adc9 pta4/kbi4 ptd3/adc8 ptb0/adc0 ptb1/adc1 ptd1/adc10 ptb2/adc2 ptb3/adc3 ptd0/adc11 ptb4/adc4 irq pta0/kbi0 vss osc1 osc2/rcclk/pta6/kbi6 pta1/kbi1 vdd pta2/kbi2 pta3/kbi3 ptb7/adc7 ptb6/adc6 ptb5/adc5 ptd7/rxd ptd6/txd pins not availabl e on 28-pin packages pte0/t2ch0 pte1/t2ch1 adc12/t2clk pta7/kbi7 internal pads are unconnected. set these unused port i/os to output low. 1 2 3 4 5 6 7 20 19 18 17 16 15 14 13 12 11 8 9 10 rst ptd4/t1ch0 ptd5/t1ch1 ptd2/adc9 ptd3/adc8 ptb0/adc0 ptb1/adc1 ptb2/adc2 ptb3/adc3 ptb4/adc4 irq vss osc1 osc2/rcclk/pta6/kbi6 vdd ptb7/adc7 ptb6/adc6 ptb5/adc5 ptd7/rxd ptd6/txd pins not available on 20-pin packages pta0/kbi0 ptd0/adc11 pta1/kbi1 ptd1/adc10 pta2/kbi2 pta3/kbi3 pte0/t2ch0 pta4/kbi4 pte1/t2ch1 pta5/kbi5 adc12/t2clk pta7/kbi7 internal pads are unconnected. set these unused port i/os to output low. the 20-pin mc68hc908jl8 is designated mc68hc908jk8. general description mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 22 freescale semiconductor table 1-2. pin functions pin name pin description in/out voltage level vdd power supply. in 5v or 3v vss power supply ground. out 0v rst reset input, active low; with internal pull-up and schmitt trigger input. in/out vdd irq external irq pin; with programmable internal pull-up and schmitt trigger input. in vdd used for monitor mode entry. in vdd to v tst osc1 crystal or rc oscillator input. in vdd osc2/rcclk osc2: crystal oscillator output; inverted osc1 signal. out vdd rcclk: rc oscillator clock output. out vdd pin as pta6/kbi6 (see pta0?pta7). in/out vdd adc12/t2clk adc12: channel-12 inpu t of adc. in vss to vdd t2clk: external input clock for tim2. in vdd pta0?pta7 8-bit general purpose i/o port. in/out vdd each pin has programmable internal pull-up when configured as input. in vdd pins as keyboard interrupts, kbi0?kbi7. in vdd pta0?pta5 and pta7 have led direct sink capability. out vss pta6 as osc2/rcclk. out vdd ptb0?ptb7 8-bit general purpose i/o port. in/out vdd pins as adc input channels, adc0?adc7. in vss to vdd ptd0?ptd7 8-bit general purpose i/o port; with programmable internal pull-ups on ptd6?ptd7. in/out vdd ptd0?ptd3 as adc input channel s, adc11?adc8. i nput vss to vdd ptd2?ptd3 and ptd6?ptd7 have le d direct sink capability out vss ptd4 as t1ch0 of tim1. in/out vdd ptd5 as t1ch1 of tim1. in/out vdd ptd6?ptd7 have configurable 25ma open-drain output. out vss ptd6 as txd of sci. out vdd ptd7 as rxd of sci. in vdd pin functions mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 23 note devices in 28-pin packages, the following pins are not available: pta7/kbi7, pte0/t2ch0, pte1/t2ch1, and adc12/t2clk. devices in 20-pin packages, the following pins are not available: pta0/kbi0?pta5/kbi5, ptd0/adc11, ptd1/adc10, pta7/kbi7, pte0/t2ch0, pte1/t2ch1, and adc12/t2clk. pte0?pte1 2-bit general purpose i/o port. in/out vdd pte0 as t2ch0 of tim2. in/out vdd pte1 as t2ch1 of tim2. in/out vdd table 1-2. pin functions (continued) pin name pin description in/out voltage level general description mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 24 freescale semiconductor mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 25 chapter 2 memory 2.1 introduction the cpu08 can address 64-kbytes of memory space. the memory map, shown in figure 2-1 , includes: 8,192 bytes of user flash memory 36 bytes of user-defined vectors 959 bytes of monitor rom 2.2 i/o section addresses $0000?$003f, shown in figure 2-2 , contain most of the control, status, and data registers. additional i/o registers have the following addresses: $fe00; break status register, bsr $fe01; reset status register, rsr $fe02; reserved $fe03; break flag control register, bfcr $fe04; interrupt status register 1, int1 $fe05; interrupt status register 2, int2 $fe06; interrupt status register 3, int3 $fe07; reserved $fe08; flash control register, flcr $fe09; reserved $fe0a; reserved $fe0b; reserved $fe0c; break address register high, brkh $fe0d; break address register low, brkl $fe0e; break status and control register, brkscr $fe0f; reserved $ffcf; flash block protect register, flbpr (flash register) $ffd0; mask option register, mor (flash register) $ffff; cop control register, copctl 2.3 monitor rom the 959 bytes at addresses $fc00?$fdff and $fe10?$ffce are reserved rom addresses that contain the instructions for the monitor functions. (see chapter 7 monitor rom (mon) .) memory mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 26 freescale semiconductor $0000 monitor rom mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 27 addr.register name bit 7654321bit 0 $0000 port a data register (pta) read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 unimplemented read: write: $0003 port d data register (ptd) read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset $0004 data direction register a (ddra) read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0006 unimplemented read: write: $0007 data direction register d (ddrd) read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 $0008 port e data register (pte) read: pte1 pte0 write: reset: unaffected by reset $0009 unimplemented read: write: $000a port d control register (pdcr) read: 0000 slowd7 slowd6 ptdpu7 ptdpu6 write: reset: 00000000 $000b unimplemented read: write: $000c data direction register e (ddre) read: ddre1 ddre0 write: reset:00000000 $000d port a input pull-up enable register (ptapue) read: pta6en ptapue6 ptapue5 ptapue4 ptapue3 ptapue2 ptapue1 ptapue0 write: reset: 00000000 $000e pta7 input pull-up enable register (pta7pue) read: ptapue7 write: reset: 00000000 $000f $0012 unimplemented read: write: u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 1 of 5) memory mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 28 freescale semiconductor $0013 sci control register 1 (scc1) read: loops ensci txinv m wake ilty pen pty write: reset:00000000 $0014 sci control register 2 (scc2) read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 $0015 sci control register 3 (scc3) read: r8 t8 dmare dmate orie neie feie peie write: reset:uu000000 $0016 sci status register 1 (scs1) read: scte tc scrf idle or nf fe pe write: reset:11000000 $0017 sci status register 2 (scs2) read: bkf rpf write: reset:00000000 $0018 sci data register (scdr) read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0019 sci baud rate register (scbr) read: scp1 scp0 r scr2 scr1 scr0 write: reset:00000000 $001a keyboard status and control register (kbscr) read: 0000 keyf 0 imaskk modek write: ackk reset: 00000000 $001b keyboard interrupt enable register (kbier) read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset: 00000000 $001c unimplemented read: write: $001d irq status and control register (intscr) read:0000irqf0 imask mode write: ack reset:00000000 $001e configuration register 2 (config2) ? read: irqpudrrlvit1lvit0rr stop_ iclkdis write: reset:0000*0*000 $001f configuration register 1 (config1) ? read: coprs r r lvid r ssrec stop copd write: reset:00000000 ? one-time writable register after each reset. * lvit1 and lvit0 reset to logic 0 by a power-on reset (por) only. $0020 tim1 status and control register (t1sc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset: 00100000 $0021 tim1 counter register high (t1cnth) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: 00000000 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 2 of 5) monitor rom mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 29 $0022 tim1 counter register low (t1cntl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: 00000000 $0023 tim counter modulo register high (tmodh) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: 11111111 $0024 tim1 counter modulo register low (t1modl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: 11111111 $0025 tim1 channel 0 status and control register (t1sc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset: 00000000 $0026 tim1 channel 0 register high (t1ch0h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $0027 tim1 channel 0 register low (t1ch0l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset $0028 tim1 channel 1 status and control register (t1sc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset: 00000000 $0029 tim1 channel 1 register high (t1ch1h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $002a tim1 channel 1 register low (t1ch1l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset $002b $002f unimplemented read: write: $0030 tim2 status and control register (t2sc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset: 00100000 $0031 tim2 counter register high (t2cnth) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: 00000000 $0032 tim2 counter register low (t2cntl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: 00000000 $0033 tim2 counter modulo register high (t2modh) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: 11111111 $0034 tim2 counter modulo register low (t2modl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: 11111111 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 3 of 5) memory mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 30 freescale semiconductor $0035 tim2 channel 0 status and control register (t2sc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset: 00000000 $0036 tim2 channel 0 register high (t2ch0h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $0037 tim2 channel 0 register low (t2ch0l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset $0038 tim2 channel 1 status and control register (t2sc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset: 00000000 $0039 tim2 channel 1 register high (t2ch1h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $003a tim2 channel 1 register low (t2ch1l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset $003b unimplemented read: write: $003c adc status and control register (adscr) read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 $003d adc data register (adr) read:ad7ad6ad5ad4ad3ad2ad1ad0 write: reset: indeterminate after reset $003e adc input clock register (adiclk) read: adiv2 adiv1 adiv0 00000 write: reset:00000000 $003f unimplemented read: write: $fe00 break status register (bsr) read: rrrrrr sbsw r write: see note reset: 0 note: writing a logic 0 clears sbsw. $fe01 reset status register (rsr) read: por pin cop ilop ilad modrst lvi 0 write: por:10000000 $fe02 reserved read: rrrrrrrr write: $fe03 break flag control register (bfcr) read: bcferrrrrrr write: reset: 0 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 4 of 5) monitor rom mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 31 $fe04 interrupt status register 1 (int1) read: if6 if5 if4 if3 0 if1 0 0 write:rrrrrrrr reset:00000000 $fe05 interrupt status register 2 (int2) read: if14 if13 if12 if11 0 0 if8 if7 write:rrrrrrrr reset:00000000 $fe06 interrupt status register 3 (int3) read:0000000if15 write:rrrrrrrr reset:00000000 $fe07 reserved read: rrrrrrrr write: $fe08 flash control register (flcr) read:0000 hven mass erase pgm write: reset:00000000 $fe09 $fe0b reserved read: rrrrrrrr write: $fe0c break address high register (brkh) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 $fe0d break address low register (brkl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:00000000 $fe0e break status and control register (brkscr) read: brke brka 000000 write: reset:00000000 $ffcf flash block protect register (flbpr) # read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset: unaffected by reset; $ff when blank $ffd0 mask option register (mor) # read: oscselrrrrrrr write: reset: unaffected by reset; $ff when blank # non-volatile flash registers; write by programming. $ffff cop control register (copctl) read: low byte of reset vector write: writing clears cop counter (any value) reset: unaffected by reset addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 5 of 5) memory mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 32 freescale semiconductor . table 2-1. vector addresses vector priority int flag address vector lowest highest ? $ffd0 random-access memory (ram) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 33 2.4 random-access memory (ram) addresses $0060 through $015f are ram locations. t he location of the stack ram is programmable. the 16-bit stack pointer allows the stack to be anywhere in the 64-kbyte memory space. note for correct operation, the stack pointer must point only to ram locations. within page zero are 160 bytes of ram. because the location of the stack ram is programmable, all page zero ram locations can be used for i/o control and us er data or code. when the stack pointer is moved from its reset location at $00ff, direct addressing mode instructions can access efficiently all page zero ram locations. page zero ram, therefore, provid es ideal locations for frequently accessed global variables. before processing an interrupt, the cpu uses five bytes of the stack to save the contents of the cpu registers. note for m6805 compatibility, the h register is not stacked. during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack pointer decrements during pushes and increments during pulls. note be careful when using nested subrouti nes. the cpu may overwrite data in the ram during a subroutine or during the interrupt stacking operation. 2.5 flash memory this sub-section describes the operation of the embedded flash memory. the flash memory can be read, programmed, and erased from a single extern al supply. the program and erase operations are enabled through the use of an internal charge pump. 2.6 functional description the flash memory consists of an array of 8,192 bytes for user memory plus a block of 36 bytes for user interrupt vectors. an erased bit reads as logic 1 and a programmed bit reads as a logic 0 . the flash memory page size is defined as 64 bytes, and is th e minimum size that can be erased in a page erase operation. program and erase operations are facilitat ed through control bits in flash control register (flcr). the address ranges for the flash memory are: $dc00?$fbff; user memory; 12,288 bytes $ffdc?$ffff; user interrupt vectors; 36 bytes programming tools are available from motorola. cont act your local motorola representative for more information. note a security feature prevents viewing of the flash contents. (1) 1. no security feature is absolutely secure . however, motorola?s strategy is to make reading or copying the flash difficult for unauthorized users. memory mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 34 freescale semiconductor 2.7 flash control register the flash control register (fclr) controls flash program and erase operations. hven ? high voltage enable bit this read/write bit enables the charge pump to dr ive high voltages for program and erase operations in the array. hven can only be set if either pgm = 1 or erase = 1 and the proper sequence for program or erase is followed. 1 = high voltage enabled to array and charge pump on 0 = high voltage disabled to array and charge pump off mass ? mass erase control bit this read/write bit configures the memory for ma ss erase operation or page erase operation when the erase bit is set. 1 = mass erase operation selected 0 = page erase operation selected erase ? erase control bit this read/write bit configures t he memory for erase operation. erase is interlocked with the pgm bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = erase operation selected 0 = erase operation not selected pgm ? program control bit this read/write bit configures the memory for progr am operation. pgm is interlocked with the erase bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = program operation selected 0 = program operation not selected 2.8 flash page erase operation use the following procedure to erase a page of flas h memory. a page consists of 64 consecutive bytes starting from addresses $xx00, $xx40, $xx80 or $xxc0. the 36-byte user interrupt vectors area also forms a page. any page within the 8,192 bytes user memory area ($dc00?$fbff) can be erased alone. the 36-byte user interrupt vectors cannot be erased by the page erase operation because of security reasons. mass erase is r equired to erase this page. 1. set the erase bit and clear the mass bit in the flash control register. 2. read the flash block protect register. 3. write any data to any flash address within the page address range desired. 4. wait for a time, t nvs (10 address: $fe08 bit 7654321bit 0 read:0000 hven mass erase pgm write: reset:00000000 figure 2-3. flash control register (flcr) flash mass erase operation mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 35 7. clear the erase bit. 8. wait for a time, t nvh (5 note programming and erasing of flash locations cannot be performed by code being executed from the flash memory. while these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. 2.9 flash mass erase operation use the following procedure to erase the entire flash memory: 1. set both the erase bit and the mass bit in the flash control register. 2. read the flash block protect register. 3. write any data to any flash location within the flash memory address range. 4. wait for a time, t nvs (10 note programming and erasing of flash locations cannot be performed by code being executed from the flash memory. while these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. 2.10 flash program operation programming of the flash memory is done on a row basis. a row consists of 32 consecutive bytes starting from addresses $xx00, $xx20, $xx40, $ xx60, $xx80, $xxa0, $xxc0 or $xxe0. use this step-by-step procedure to program a row of flash memory: ( figure 2-4 shows a flowchart of the programming algorithm.) 1. set the pgm bit. this configures the memory for program operation and enables the latching of address and data for programming. 2. read the flash block protect register. 3. write any data to any flash location within the address range of the row to be programmed. 4. wait for a time, t nvs (10 memory mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 36 freescale semiconductor 8. wait for time, t prog (30 note the time between each flash address change (step 7 to step 7), or the time between the last flash addres sed programmed to clearing the pgm bit (step 7 to step 10), must not exceed the maximum programming time, t prog max. note programming and erasing of flash locations cannot be performed by code being executed from the flash memory. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. flash program operation mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 37 figure 2-4. flash programming flowchart set hven bit read the flash block protect register write any data to any flash location within the address range of the row to wait for a time, t nvs set pgm bit wait for a time, t pgs write data to the flash address to be programmed wait for a time, t prog clear pgm bit wait for a time, t nvh clear hven bit wait for a time, t rcv completed programming this row? y n end of programming the time between each flash address change (step 7 to step 7), or must not exceed the maximum programming time, t prog max. the time between the last flash address programmed to clearing pgm bit (step 7 to step 10) note: 1 2 3 4 5 6 7 8 10 11 12 13 algorithm for programming a row (32 bytes) of flash memory this row program algorithm assumes the row/s to be programmed are initially erased. be programmed memory mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 38 freescale semiconductor 2.11 flash block protection due to the ability of the on-board charge pump to erase and program the flash memory in the target application, provision is made to protect blocks of memory from unintentional erase or program operations due to system malfunction. this protection is done by use of a flash block protect register (flbpr). the flbpr determines the range of the flash memory which is to be protected. the range of the protected area starts from a location defined by flbpr and ends to the bottom of the flash memory ($ffff). when the memory is protected, the hven bit cannot be set in either erase or program operations. note in performing a program or erase operation, the flash block protect register must be read after setting the pgm or erase bit and before asserting the hven bit when the flbpr is program with all 0?s, the entir e memory is protected from being programmed and erased. when all the bits are erased (all 1?s), the entire memory is accessible for program and erase. when bits within the flbpr are programmed, they lock a block of memory, address ranges as shown in 2.12 flash block protect register . once the flbpr is programmed with a value other than $ff, any erase or program of the flbpr or the protected block of flash memory is prohibited. the flbpr itself can be erased or programmed only with an external voltage, v tst , present on the irq pin. this voltage also allows entry from re set into the monitor mode. 2.12 flash block protect register the flash block protect register (flbpr) is impl emented as a byte within the flash memory, and therefore can only be written during a programming sequence of the flash memory. the value in this register determines the starting location of the protected range within the flash memory. bpr[7:0] ? flash block protect bits bpr[7:0] represent bits [13:6] of a 16-bit memory addr ess. bits [15:14] are logic 1?s and bits [5:0] are logic 0?s. address: $ffcf bit 7654321bit 0 read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset: unaffected by reset; $ff when blank non-volatile flash register; write by programming. figure 2-5. flash block protect register (flbpr) 16-bit memory address start address of flash block protect 1 1 000000 bpr[7:0] flash block protect register mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 39 the resultant 16-bit address is used for specifying the start address of the flash memory for block protection. the flash is protected from this star t address to the end of flash memory, at $ffff. with this mechanism, the protect start address can be xx00, xx40, xx80, or xxc0 (at page boundaries ? 64 bytes) within the flash memory. examples of protect start address: bpr[7:0] start of address of protect range (1) 1. the end address of the prot ected range is always $ffff. $00?$70 the entire flash memory is protected. $71 ( 0111 0001 ) $dc40 (11 01 1100 01 00 0000) $72 ( 0111 0010 ) $dc80 (11 01 1100 10 00 0000) $73 ( 0111 0011 ) $dcc0 (11 01 1100 11 00 0000) and so on... $fd ( 1111 1101 ) $ff40 (11 11 1111 01 00 0000) $fe ( 1111 1110 ) $ff80 (11 11 1111 10 00 0000) $ff the entire flash memory is not protected. memory mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 40 freescale semiconductor mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 41 chapter 3 configuration and mask option registers (config & mor) 3.1 introduction this section describes the configuration registers, config1 and config2; and the mask option register (mor). the configuration registers enable or disable these options: computer operating properly module (cop) cop timeout period (2 13 ?2 4 or 2 18 ?2 4 note the options except lvit[1:0] are one-time writable by the user after each reset. the lvit[1:0] bits are one-time writable by the user only after each por (power-on reset). the config registers are not in the flash memory but are special registers containing one-time writable latches after each reset. upon a reset, the config registers default to predetermined settings as shown in figure 3-1 and figure 3-2. the mask option register (mor) is used to select t he oscillator option for the mcu: crystal oscillator or rc oscillator. the mor is implemented as a byte in flash memory. hence, writing to the mor requires programming the byte. configuration and mask opti on registers (config & mor) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 42 freescale semiconductor 3.3 configuration register 1 (config1) coprs ? cop rate select bit coprs selects the cop time-out period. reset clears coprs. (see chapter 14 computer operating properly (cop) .) 1 = cop timeout period is (2 13 ? 2 4 ) note exiting stop mode by pulling reset will result in the long stop recovery. if using an external crystal, do not set the ssrec bit. stop ? stop instruction enable bit stop enables the stop instruction. 1 = stop instruction enabled 0 = stop instruction treated as illegal opcode copd ? cop disable bit copd disables the cop module. reset clears copd. (see chapter 14 computer operating properly (cop) .) 1 = cop module disabled 0 = cop module enabled address: $001f bit 7654321bit 0 read: coprs r r lvid r ssrec stop copd write: reset:00000000 r=reserved figure 3-1. configuration register 1 (config1) configuration register 2 (config2) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 43 3.4 configuration register 2 (config2) irqpud ? irq pin pull-up disable bit irqpud disconnects the internal pull-up on the irq pin. 1 = internal pull-up is disconnected 0 = internal pull-up is connected between irq pin and v dd lvit1, lvit0 ? lvi trip voltage selection bits detail description of trip voltage selection is given in chapter 15 low voltage inhibit (lvi) . stop_iclkdis ? internal oscillator stop mode disable bit setting stop_iclkdis disables the in ternal oscillator during stop mode. when this bit is cleared, the internal oscillator continues to operate in stop mode. reset clears this bit. 1 = internal oscillator disabled during stop mode 0 = internal oscillator enabled during stop mode 3.5 mask option register (mor) the mask option register (mor) is implemented as a byte within the flash memory, and therefore can only be written during a programming sequence of the flash memory. this register is read after a power-on reset to determine the type of oscillator selected. (see chapter 6 oscillator (osc) .) oscsel ? oscillator select bit oscsel selects the oscillator type for the mcu. the erased or unprogrammed state of this bit is logic 1, selecting the crystal oscillator option. this bit is unaffected by reset. 1 = crystal oscillator 0 = rc oscillator address: $001e bit 7654321bit 0 read: irqpud r r lvit1 lvit0 r r stop_ iclkdis write: reset:000 not affected not affected 000 por:00000000 r=reserved one-time writable register after each reset. lvit1 and lvit0 reset to logic 0 by a power-on reset (por) only. figure 3-2. configuration register 2 (config2) address: $ffd0 bit 7654321bit 0 read: oscselrrrrrrr write: erased:11111111 reset: unaffected by reset non-volatile flash register; write by programming. r=reserved figure 3-3. mask option register (mor) configuration and mask opti on registers (config & mor) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 44 freescale semiconductor bits 6?0 ? should be left as logic 1?s. note when crystal oscillator is selected, the osc2/rcclk/pta6/kbi6 pin is used as osc2; other functions such as pta6/kbi6 will not be available. mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 45 chapter 4 central processor unit (cpu) 4.1 introduction the m68hc08 cpu (central processor unit) is an e nhanced and fully object-code- compatible version of the m68hc05 cpu. the cpu08 reference manual (motorola document order number cpu08rm/ad) contains a description of the cpu instruction set, addressing modes, and architecture. 4.2 features object code fully upward-compatible with m68hc05 family 16-bit stack pointer with stack manipulation instructions 16-bit index register with x-r egister manipulation instructions 8-mhz cpu internal bus frequency 64-kbyte program/data memory space 16 addressing modes memory-to-memory data moves without using accumulator fast 8-bit by 8-bit multiply and 16 -bit by 8-bit divide instructions enhanced binary-coded decimal (bcd) data handling modular architecture with expandable internal bus definition for extension of addressing range beyond 64 kbytes low-power stop and wait modes central processor unit (cpu) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 46 freescale semiconductor 4.3 cpu registers figure 4-1 shows the five cpu registers. cpu registers are not part of the memory map. figure 4-1. cpu registers 4.3.1 accumulator the accumulator is a general-purpose 8-bit register. the cpu uses the accumulator to hold operands and the results of arithmetic/logic operations. 4.3.2 index register the 16-bit index register allows i ndexed addressing of a 64-kbyte memory space. h is the upper byte of the index register, and x is the lower byte. h:x is the concatenated 16-bit index register. in the indexed addressing modes, th e cpu uses the contents of the index register to determine the conditional address of the operand. the index register can serve also as a temporary data storage location. bit 7654321bit 0 read: write: reset: unaffected by reset figure 4-2. accumulator (a) accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag two?s complement overflow flag v11hinzc h x 0 0 0 0 7 15 15 15 70 cpu registers mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 47 4.3.3 stack pointer the stack pointer is a 16-bit register that contains the address of the next location on the stack. during a reset, the stack pointer is preset to $00ff. the reset stack pointer (rsp) instruction sets the least significant byte to $ff and does not affect the most significant byte. the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bit offset and 16-bit offset a ddressing modes, the stack pointer can function as an index register to access data on t he stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. note the location of the stack is arbitrary and may be relocated anywhere in ram. moving the sp out of page 0 ($0000 to $00ff) frees direct address (page 0) space. for correct operation, the stack pointer must point only to ram locations. 4.3.4 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter automatically increm ents to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vector address is the address of the first instruction to be executed after exiting the reset state. bit 15 1413121110987654321bit 0 read: write: reset:00000000 xxxxxxxx x = indeterminate figure 4-3. index register (h:x) bit 15 1413121110987654321bit 0 read: write: reset:0000000011111111 figure 4-4. stack pointer (sp) central processor unit (cpu) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 48 freescale semiconductor 4.3.5 condition code register the 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. bits 6 and 5 are set perm anently to logic 1. the fo llowing paragraphs describe the functions of the condition code register. v ? overflow flag the cpu sets the overflow flag when a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow h ? half-carry flag the cpu sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (add) or add-with-carry (adc) operation. the half-carry flag is required for binary-coded decimal (bcd) arithmetic operations. th e daa instruction uses the states of the h and c flags to determine the appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 i ? interrupt mask when the interrupt mask is set, all maskable cp u interrupts are disabled. cpu interrupts are enabled when the interrupt mask is cleared. when a cpu interrupt occurs, the interrupt mask is set automatically after the cpu registers are saved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled note to maintain m6805 family compatibil ity, the upper byte of the index register (h) is not stacked automatically. if the interrupt service routine modifies h, then the user must stack and unstack h using the pshh and pulh instructions. bit 15 1413121110987654321bit 0 read: write: reset: loaded with vector from $fffe and $ffff figure 4-5. program counter (pc) bit 7654321bit 0 read: v11hinzc write: reset:x11x1xxx x = indeterminate figure 4-6. condition code register (ccr) arithmetic/logic unit (alu) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 49 after the i bit is cleared, the highest-priori ty interrupt request is serviced first. a return-from-interrupt (rti) instruction pulls the cpu registers from the stack and restores the interrupt mask from the stack. after any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (cli). n ? negative flag the cpu sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result z ? zero flag the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = zero result 0 = non-zero result c ? carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some instructions ? such as bit test and branch, shift, and rotate ? also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7 4.4 arithmetic/logic unit (alu) the alu performs the arithmetic and logic operations defined by the instruction set. refer to the cpu08 reference manual (motorola document order number cpu08rm/ad) for a description of the instructions and addressing modes and more detail about the architecture of the cpu. 4.5 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 4.5.1 wait mode the wait instruction: clears the interrupt mask (i bit) in the condition code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains cl ear. after exit by reset, the i bit is set. disables the cpu clock 4.5.2 stop mode the stop instruction: clears the interrupt mask (i bit) in the conditi on code register, enabling external interrupts. after exit from stop mode by external interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock after exiting stop mode, the cpu clock begins ru nning after the oscillator stabilization delay. central processor unit (cpu) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 50 freescale semiconductor 4.6 cpu during break interrupts if a break module is present on the mcu, the cpu starts a break interrupt by: loading the instruction register with the swi instruction loading the program counter with $fffc:$fffd or with $fefc:$fefd in monitor mode the break interrupt begins after completion of the cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu in struction, the break inte rrupt begins immediately. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation if the break interrupt has been deasserted. 4.7 instruction set summary table 4-1 provides a summary of the m68hc08 instruction set. 4.8 opcode map the opcode map is provided in table 4-2 . table 4-1. instruction set summary source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a r r ? r r r imm dir ext ix2 ix1 ix sp1 sp2 a9 b9 c9 d9 e9 f9 9ee9 9ed9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 add # opr add opr add opr add opr ,x add opr ,x add ,x add opr ,sp add opr ,sp add without carry a r r ? r r r imm dir ext ix2 ix1 ix sp1 sp2 ab bb cb db eb fb 9eeb 9edb ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ais # opr add immediate value (signed) to sp sp opr add immediate value (signed) to h:x h:x opcode map mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 51 and # opr and opr and opr and opr ,x and opr ,x and ,x and opr ,sp and opr ,sp logical and a r r ? imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) r ?? r r r dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 asr opr asra asrx asr opr ,x asr opr ,x asr opr ,sp arithmetic shift right r ?? r r r dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 4 1 1 4 3 5 bcc rel branch if carry bit clear pc n , opr clear bit n in m mn rel branch if carry bit set (same as blo) pc rel ? (c) = 1 ??????rel 25 rr 3 beq rel branch if equal pc rel ? (z) = 1 ??????rel 27 rr 3 bge opr branch if greater than or equal to (signed operands) pc rel ? (n opr branch if greater than (signed operands) pc rel ? (z) rel branch if half carry bit clear pc rel ? (h) = 0 ??????rel 28 rr 3 bhcs rel branch if half carry bit set pc rel ? (h) = 1 ??????rel 29 rr 3 bhi rel branch if higher pc rel ? (c) | (z) = 0 ??????rel 22 rr 3 bhs rel branch if higher or same (same as bcc) pc rel ? (c) = 0 ??????rel 24 rr 3 bih rel branch if irq pin high pc rel ? irq = 1 ??????rel 2f rr 3 bil rel branch if irq pin low pc rel ? irq = 0 ??????rel 2e rr 3 table 4-1. instruction set summary source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0 b0 b7 c central processor unit (cpu) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 52 freescale semiconductor bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit opr ,sp bit opr ,sp bit test (a) & (m) 0 ? ? r r ? imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc rel ? (z) rel branch if lower (same as bcs) pc rel ? (c) = 1 ??????rel 25 rr 3 bls rel branch if lower or same pc rel ? (c) | (z) = 1 ??????rel 23 rr 3 blt opr branch if less than (signed operands) pc rel ? (n rel branch if interrupt mask clear pc rel ? (i) = 0 ??????rel 2c rr 3 bmi rel branch if minus pc rel ? (n) = 1 ??????rel 2b rr 3 bms rel branch if interrupt mask set pc rel ? (i) = 1 ??????rel 2d rr 3 bne rel branch if not equal pc rel ? (z) = 0 ??????rel 26 rr 3 bpl rel branch if plus pc rel ? (n) = 0 ??????rel 2a rr 3 bra rel branch always pc rel ??????rel 20 rr 3 brclr n , opr , rel branch if bit n in m clear pc rel ? (mn) = 0 ? ? ? ? ? r dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc n , opr , rel branch if bit n in m set pc rel ? (mn) = 1 ? ? ? ? ? r dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n , opr set bit n in m mn opcode map mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 53 bsr rel branch to subroutine pc rel ??????rel ad rr 4 cbeq opr,rel cbeqa # opr,rel cbeqx # opr,rel cbeq opr, x+ ,rel cbeq x+ ,rel cbeq opr, sp ,rel compare and branch if equal pc opr clra clrx clrh clr opr ,x clr ,x clr opr ,sp clear m opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x cmp opr ,sp cmp opr ,sp compare a with m (a) ? (m) r ?? r r r imm dir ext ix2 ix1 ix sp1 sp2 a1 b1 c1 d1 e1 f1 9ee1 9ed1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 com opr coma comx com opr ,x com ,x com opr ,sp complement (one?s complement) m r r 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 4 1 1 4 3 5 cphx # opr cphx opr compare h:x with m (h:x) ? (m:m + 1) r ?? r r r imm dir 65 75 ii ii+1 dd 3 4 cpx # opr cpx opr cpx opr cpx ,x cpx opr ,x cpx opr ,x cpx opr ,sp cpx opr ,sp compare x with m (x) ? (m) r ?? r r r imm dir ext ix2 ix1 ix sp1 sp2 a3 b3 c3 d3 e3 f3 9ee3 9ed3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 daa decimal adjust a (a) 10 u?? r r r inh 72 2 table 4-1. instruction set summary source form operation description effect on ccr address mode opcode operand cycles vh i nzc central processor unit (cpu) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 54 freescale semiconductor dbnz opr,rel dbnza rel dbnzx rel dbnz opr, x ,rel dbnz x ,rel dbnz opr, sp ,rel decrement and branch if not zero a rel ? (result) rel ? (result) rel ? (result) rel ? (result) rel ? (result) rel ? (result) opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m r ?? r r ? dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a r r inh 52 7 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x eor opr ,sp eor opr ,sp exclusive or m with a a r r ? imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m r ?? r r ? dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc n ( n = 1, 2, or 3) push (pcl); sp opr lda opr lda opr lda opr ,x lda opr ,x lda ,x lda opr ,sp lda opr ,sp load a from m a r r ? imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ldhx # opr ldhx opr load h:x from m h:x r r ? imm dir 45 55 ii jj dd 3 4 table 4-1. instruction set summary source form operation description effect on ccr address mode opcode operand cycles vh i nzc opcode map mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 55 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x r r ? imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp logical shift left (same as asl) r ?? r r r dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 lsr opr lsra lsr x lsr opr ,x lsr ,x lsr opr ,sp logical shift right r ??0 r r dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 4 1 1 4 3 5 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination r r ? dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a opr nega negx neg opr ,x neg ,x neg opr ,sp negate (two?s complement) m r ?? r r r dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 4 1 1 4 3 5 nop no operation none ??????inh 9d 1 nsa nibble swap a a opr ora opr ora opr ora opr ,x ora opr ,x ora ,x ora opr ,sp ora opr ,sp inclusive or a and m a r r ? imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9eda ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 psha push a onto stack push (a); sp ( ) central processor unit (cpu) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 56 freescale semiconductor pulh pull h from stack sp ( ) ( ) opr rola rolx rol opr ,x rol ,x rol opr ,sp rotate left through carry r ?? r r r dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 4 1 1 4 3 5 ror opr rora rorx ror opr ,x ror ,x ror opr ,sp rotate right through carry r ?? r r r dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 4 1 1 4 3 5 rsp reset stack pointer sp r r r r r r inh 80 7 rts return from subroutine sp ; ( opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a r ?? r r r imm dir ext ix2 ix1 ix sp1 sp2 a2 b2 c2 d2 e2 f2 9ee2 9ed2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 sec set carry bit c opr sta opr sta opr ,x sta opr ,x sta ,x sta opr ,sp sta opr ,sp store a in m m r r ? dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m (m:m + 1) r r ? dir 35 dd 4 stop enable irq pin; stop oscillator i opcode map mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 57 stx opr stx opr stx opr ,x stx opr ,x stx ,x stx opr ,sp stx opr ,sp store x in m m r r ? dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a r ?? r r r imm dir ext ix2 ix1 ix sp1 sp2 a0 b0 c0 d0 e0 f0 9ee0 9ed0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 swi software interrupt pc r r r r r r inh 84 2 tax transfer a to x x opr tsta tstx tst opr ,x tst ,x tst opr ,sp test for negative or zero (a) ? $00 or (x) ? $00 or (m) ? $00 0 ? ? r r ? dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x central processor unit (cpu) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 58 freescale semiconductor a accumulator n any bit c carry/borrow bit opr operand (one or two bytes) ccr condition code register pc program counter dd direct address of operand pch program counter high byte dd rr direct address of operand and relative offset of branch instruction pcl program counter low byte dd direct to direct addressing mode rel relative addressing mode dir direct addressing mode rel relative program counter offset byte dix+ direct to indexed with pos t increment addressing mode rr relati ve program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offset addressing sp1 stack pointer , 8-bit offset addressing mode ext extended addressing mode sp2 stack poi nter 16-bit offset addressing mode ff offset byte in indexed, 8-bit offset addressing sp stack pointer h half-carry bit u undefined h index register high byte v overflow bit hh ll high and low bytes of operand address in ex tended addressing x index register low byte i interrupt mask z zero bit ii immediate operand byte & logical and imd immediate source to direct de stination addressing mode | logical or imm immediate addressing mode r set or cleared n negative bit ? not affected table 4-1. instruction set summary source form operation description effect on ccr address mode opcode operand cycles vh i nzc mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 59 opcode map table 4-2. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 sp1 ix inh inh imm dir ext ix2 sp2 ix1 sp1 ix 0 1234569e6789abcd9ede9eef 0 5 brset0 3dir 4 bset0 2dir 3 bra 2rel 4 neg 2dir 1 nega 1inh 1 negx 1inh 4 neg 2ix1 5 neg 3sp1 3 neg 1ix 7 rti 1inh 3 bge 2rel 2 sub 2imm 3 sub 2dir 4 sub 3ext 4 sub 3ix2 5 sub 4sp2 3 sub 2ix1 4 sub 3sp1 2 sub 1ix 1 5 brclr0 3dir 4 bclr0 2dir 3 brn 2rel 5 cbeq 3dir 4 cbeqa 3imm 4 cbeqx 3imm 5 cbeq 3ix1+ 6 cbeq 4sp1 4 cbeq 2ix+ 4 rts 1inh 3 blt 2rel 2 cmp 2imm 3 cmp 2dir 4 cmp 3ext 4 cmp 3ix2 5 cmp 4sp2 3 cmp 2ix1 4 cmp 3sp1 2 cmp 1ix 2 5 brset1 3dir 4 bset1 2dir 3 bhi 2rel 5 mul 1inh 7 div 1inh 3 nsa 1inh 2 daa 1inh 3 bgt 2rel 2 sbc 2imm 3 sbc 2dir 4 sbc 3ext 4 sbc 3ix2 5 sbc 4sp2 3 sbc 2ix1 4 sbc 3sp1 2 sbc 1ix 3 5 brclr1 3dir 4 bclr1 2dir 3 bls 2rel 4 com 2dir 1 coma 1inh 1 comx 1inh 4 com 2ix1 5 com 3sp1 3 com 1ix 9 swi 1inh 3 ble 2rel 2 cpx 2imm 3 cpx 2dir 4 cpx 3ext 4 cpx 3ix2 5 cpx 4sp2 3 cpx 2ix1 4 cpx 3sp1 2 cpx 1ix 4 5 brset2 3dir 4 bset2 2dir 3 bcc 2rel 4 lsr 2dir 1 lsra 1inh 1 lsrx 1inh 4 lsr 2ix1 5 lsr 3sp1 3 lsr 1ix 2 ta p 1inh 2 txs 1inh 2 and 2imm 3 and 2dir 4 and 3ext 4 and 3ix2 5 and 4sp2 3 and 2ix1 4 and 3sp1 2 and 1ix 5 5 brclr2 3dir 4 bclr2 2dir 3 bcs 2rel 4 sthx 2dir 3 ldhx 3imm 4 ldhx 2dir 3 cphx 3imm 4 cphx 2dir 1 tpa 1inh 2 tsx 1inh 2 bit 2imm 3 bit 2dir 4 bit 3ext 4 bit 3ix2 5 bit 4sp2 3 bit 2ix1 4 bit 3sp1 2 bit 1ix 6 5 brset3 3dir 4 bset3 2dir 3 bne 2rel 4 ror 2dir 1 rora 1inh 1 rorx 1inh 4 ror 2ix1 5 ror 3sp1 3 ror 1ix 2 pula 1inh 2 lda 2imm 3 lda 2dir 4 lda 3ext 4 lda 3ix2 5 lda 4sp2 3 lda 2ix1 4 lda 3sp1 2 lda 1ix 7 5 brclr3 3dir 4 bclr3 2dir 3 beq 2rel 4 asr 2dir 1 asra 1inh 1 asrx 1inh 4 asr 2ix1 5 asr 3sp1 3 asr 1ix 2 psha 1inh 1 ta x 1inh 2 ais 2imm 3 sta 2dir 4 sta 3ext 4 sta 3ix2 5 sta 4sp2 3 sta 2ix1 4 sta 3sp1 2 sta 1ix 8 5 brset4 3dir 4 bset4 2dir 3 bhcc 2rel 4 lsl 2dir 1 lsla 1inh 1 lslx 1inh 4 lsl 2ix1 5 lsl 3sp1 3 lsl 1ix 2 pulx 1inh 1 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3ext 4 eor 3ix2 5 eor 4sp2 3 eor 2ix1 4 eor 3sp1 2 eor 1ix 9 5 brclr4 3dir 4 bclr4 2dir 3 bhcs 2rel 4 rol 2dir 1 rola 1inh 1 rolx 1inh 4 rol 2ix1 5 rol 3sp1 3 rol 1ix 2 pshx 1inh 1 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3ext 4 adc 3ix2 5 adc 4sp2 3 adc 2ix1 4 adc 3sp1 2 adc 1ix a 5 brset5 3dir 4 bset5 2dir 3 bpl 2rel 4 dec 2dir 1 deca 1inh 1 decx 1inh 4 dec 2ix1 5 dec 3sp1 3 dec 1ix 2 pulh 1inh 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3ext 4 ora 3ix2 5 ora 4sp2 3 ora 2ix1 4 ora 3sp1 2 ora 1ix b 5 brclr5 3dir 4 bclr5 2dir 3 bmi 2rel 5 dbnz 3dir 3 dbnza 2inh 3 dbnzx 2inh 5 dbnz 3ix1 6 dbnz 4sp1 4 dbnz 2ix 2 pshh 1inh 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3ext 4 add 3ix2 5 add 4sp2 3 add 2ix1 4 add 3sp1 2 add 1ix c 5 brset6 3dir 4 bset6 2dir 3 bmc 2rel 4 inc 2dir 1 inca 1inh 1 incx 1inh 4 inc 2ix1 5 inc 3sp1 3 inc 1ix 1 clrh 1inh 1 rsp 1inh 2 jmp 2dir 3 jmp 3ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix d 5 brclr6 3dir 4 bclr6 2dir 3 bms 2rel 3 tst 2dir 1 tsta 1inh 1 tstx 1inh 3 tst 2ix1 4 tst 3sp1 2 tst 1ix 1 nop 1inh 4 bsr 2rel 4 jsr 2dir 5 jsr 3ext 6 jsr 3ix2 5 jsr 2ix1 4 jsr 1ix e 5 brset7 3dir 4 bset7 2dir 3 bil 2rel 5 mov 3dd 4 mov 2dix+ 4 mov 3imd 4 mov 2ix+d 1 stop 1inh * 2 ldx 2imm 3 ldx 2dir 4 ldx 3ext 4 ldx 3ix2 5 ldx 4sp2 3 ldx 2ix1 4 ldx 3sp1 2 ldx 1ix f 5 brclr7 3dir 4 bclr7 2dir 3 bih 2rel 3 clr 2dir 1 clra 1inh 1 clrx 1inh 3 clr 2ix1 4 clr 3sp1 2 clr 1ix 1 wait 1inh 1 txa 1inh 2 aix 2imm 3 stx 2dir 4 stx 3ext 4 stx 3ix2 5 stx 4sp2 3 stx 2ix1 4 stx 3sp1 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd direct-direct imd immediate-direct ix1+ indexed, 1-byte offset with ix+d indexed-direct dix+ direct-indexed post increment * pre-byte for stack pointer indexed instructions 0 high byte of opcode in hexadecimal low byte of opcode in hexadecimal 0 5 brset0 3dir cycles opcode mnemonic number of bytes / addressing mode msb lsb msb lsb central processor unit (cpu) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 60 freescale semiconductor mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 61 chapter 5 system integration module (sim) 5.1 introduction this section describes the system integration module (sim), which supports up to 24 external and/or internal interrupts. together with the cpu, the sim c ontrols all mcu activities. a block diagram of the sim is shown in figure 5-1 . figure 5-2 is a summary of the sim i/o registers. the sim is a system state controller that coordinates cpu and exception timing. the sim is responsible for: bus clock generation and control for cpu and peripherals ? stop/wait/reset/break entry and recovery ? internal clock control master reset control, including power-on reset (por) and cop timeout interrupt control: ? acknowledge timing ? arbitration control timing ? vector address generation cpu enable/disable timing modular architecture expandable to 128 interrupt sources table 5-1 shows the internal signal names used in this section. table 5-1. signal name conventions signal name description iclk internal oscillator clock oscout the xtal or rc frequency divided by two. this signal is again divided by two in the sim to generate the internal bus clocks. (bus clock = oscout 2) iab internal address bus idb internal data bus porrst signal from the power-on reset module to the sim irst internal reset signal r/w read/write signal system integration module (sim) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 62 freescale semiconductor figure 5-1. sim block diagram addr.register name bit 7654321bit 0 $fe00 break status register (bsr) read: rrrrrr sbsw r write: note reset:00000000 note: writing a logic 0 clears sbsw. $fe01 reset status register (rsr) read: por pin cop ilop ilad modrst lvi 0 write: por:10000000 $fe02 reserved read: rrrrrrrr write: reset: $fe03 break flag control register (bfcr) read: bcferrrrrrr write: reset: 0 figure 5-2. sim i/o register summary stop/wait clock control clock generators por control reset pin control sim reset status register interrupt control and priority decode module stop module wait cpu stop (from cpu) cpu wait (from cpu) simoscen (to oscillator) oscout (from oscillator) internal clocks master reset control reset pin logic illegal opcode (from cpu) illegal address (from address map decoders) cop timeout (from cop module) interrupt sources cpu interface reset control sim counter cop clock iclk (from oscillator) 2 usb reset (from usb module) vdd internal pull-up sim bus clock control and generation mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 63 5.2 sim bus clock control and generation the bus clock generator provides system clock signa ls for the cpu and peripherals on the mcu. the system clocks are generated from an incoming clock, oscout, as shown in figure 5-3 . figure 5-3. sim clock signals 5.2.1 bus timing in user mode , the internal bus frequency is the o scillator frequency divided by four. 5.2.2 clock start-up from por or lvi reset when the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the cpu and peripherals are inactive and held in an inactive phase until after the 4096 iclk cycle por timeout has completed. the rst pin is driven low by the sim during this entire period. the ibus clocks start upon completion of the timeout. 5.2.3 clocks in st op mode and wait mode upon exit from stop mode by an interrupt, break, or reset, the sim allows iclk to clock the sim counter. the cpu and peripheral clocks do not become active un til after the stop delay time-out. this time-out is selectable as 4096 or 32 iclk cycles. (see 5.6.2 stop mode .) in wait mode, the cpu clocks are inactive. the sim also produces two sets of clocks for other modules. refer to the wait mode subsection of each module to s ee if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. $fe04 interrupt status register 1 (int1) read: if6 if5 if4 if3 0 if1 0 0 write:rrrrrrrr reset:00000000 $fe05 interrupt status register 2 (int2) read: if14 if13 if12 if11 0 0 if8 if7 write:rrrrrrrr reset:00000000 $fe06 interrupt status register 3 (int3) read:0000000if15 write:rrrrrrrr reset:00000000 = unimplemented r = reserved figure 5-2. sim i/o register summary 2 bus clock generators sim sim counter from oscillator from oscillator oscout iclk oscout is osc frequency divided by 2 system integration module (sim) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 64 freescale semiconductor 5.3 reset and system initialization the mcu has these reset sources: power-on reset module (por) external reset pin (rst ) computer operating properly module (cop) low-voltage inhibit module (lvi) illegal opcode illegal address all of these resets produce the vector $fffe?$ffff ($fefe?$feff in monitor mode) and assert the internal reset signal (irst). irst causes all register s to be returned to their default values and all modules to be returned to their reset states. an internal reset clears the sim counter (see 5.4 sim counter), but an external reset does not. each of the resets sets a corresponding bit in the reset status register (rsr). (see 5.7 sim registers .) 5.3.1 external pin reset the rst pin circuits include an internal pull- up device. pulling the asynchronous rst pin low halts all processing. the pin bit of the reset status register (rsr) is set as long as rst is held low for a minimum of 67 iclk cycles, assuming that the po r was not the source of the reset. see table 5-2 for details. figure 5-4 shows the relative timing. figure 5-4. external reset timing 5.3.2 active resets from internal sources all internal reset sources actively pull the rst pin low for 32 iclk cycles to allow resetting of external peripherals. the internal reset signal irst cont inues to be asserted for an additional 32 cycles ( figure 5-5 ). an internal reset can be caused by an illegal address, illegal opcode, cop time-out, or por. (see figure 5-6 . sources of internal reset .) note that for por resets, the sim cycles through 4096 iclk cycles during which the sim forces the rst pin low. the internal reset signal then follows the sequence from the falling edge of rst shown in figure 5-5 . table 5-2. pin bit set timing reset type number of cycl es required to set pin por 4163 (4096 + 64 + 3) all others 67 (64 + 3) rst iab pc vect h vect l iclk reset and system initialization mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 65 figure 5-5. internal reset timing the cop reset is asynchronous to the bus clock. figure 5-6. sources of internal reset the active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the mcu. 5.3.2.1 power-on reset when power is first applied to the mcu, the power-on reset module (por) generates a pulse to indicate that power-on has occurred. the external reset pin (rst ) is held low while the sim counter counts out 4096 iclk cycles. sixty-four iclk cycles later, t he cpu and memories are released from reset to allow the reset vector sequence to occur. at power-on, the following events occur: a por pulse is generated. the internal reset signal is asserted. the sim enables oscout. internal clocks to the cpu and modules are held in active for 4096 iclk cycles to allow stabilization of the oscillator. the rst pin is driven low during the oscillator stabilization time. the por bit of the reset status register (rsr) is set and all other bits in the register are cleared. irst rst rst pulled low by mcu iab 32 cycles 32 cycles vector high iclk illegal address rst illegal opcode rst coprst por lvi internal reset system integration module (sim) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 66 freescale semiconductor figure 5-7. por recovery 5.3.2.2 computer operating properly (cop) reset an input to the sim is reserved for the cop reset signal. the overflow of th e cop counter causes an internal reset and sets the cop bit in the reset stat us register (rsr). the sim actively pulls down the rst pin for all internal reset sources. to prevent a cop module time-out, write any value to location $ffff. writing to location $ffff clears the cop counter and stages 12 through 5 of the sim counter. the sim counter output, which occurs at least every (2 12 ? 2 4 ) iclk cycles, drives the cop counter. the cop should be serviced as soon as possible out of reset to guarantee the maximum amount of time before the first time-out. the cop module is disabled if the rst pin or the irq pin is held at v tst while the mcu is in monitor mode. the cop module can be disabled only through combinational logic conditioned with the high voltage signal on the rst or the irq pin. this prevents the cop from becoming disabled as a result of external noise. during a break state, v tst on the rst pin disables the cop module. 5.3.2.3 illegal opcode reset the sim decodes signals from the cpu to detect illegal instructions. an illegal instruction sets the ilop bit in the reset status register (rsr) and causes a reset. if the stop enable bit, stop, in the mask option register is logic zero, the sim treats the stop instruction as an illegal opcode and causes an illegal opc ode reset. the sim actively pulls down the rst pin for all internal reset sources. 5.3.2.4 illegal address reset an opcode fetch from an unmapped address generates an illegal address reset. the sim verifies that the cpu is fetching an opcode prior to asserting the ilad bit in the reset status register (rsr) and resetting the mcu. a data fetch from an unmapped address does not generate a reset. the sim actively pulls down the rst pin for all internal reset sources. 5.3.2.5 low-voltage inhibit (lvi) reset the low-voltage inhibit module (lvi) asserts its output to the sim when the v dd voltage falls to the lvi trip voltage v trip . the lvi bit in the reset status register (rsr) is set, and the external reset pin (rst ) is porrst osc1 iclk oscout rst iab 4096 cycles 32 cycles 32 cycles $fffe $ffff sim counter mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 67 held low while the sim counter counts out 4096 iclk cycles. sixty-four iclk cycles later, the cpu and memories are released from reset to allow the reset vector sequence to occur. the sim actively pulls down the rst pin for all internal reset sources. 5.4 sim counter the sim counter is used by the power-on reset module (por) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (ibus) clocks. the sim counter also serves as a prescaler for the computer operating properly module (cop). the sim counter uses 12 stages for counting, followed by a 13th stage that triggers a reset of sim counters and supplies the clock for the cop module. the sim counter is clocke d by the falling edge of iclk. 5.4.1 sim counter during power-on reset the power-on reset module (por) detects power applied to the mcu. at power-on, the por circuit asserts the signal porrst. once the sim is initializ ed, it enables the oscillator to drive the bus clock state machine. 5.4.2 sim counter du ring stop mode recovery the sim counter also is used for stop mode recovery. the stop instruction clears the sim counter. after an interrupt, break, or reset, the sim senses the state of the short stop recovery bit, ssrec, in the mask option register. if the ssrec bit is a logic one, then the stop recovery is reduced from the normal delay of 4096 iclk cycles down to 32 iclk cycles. this is ideal for applications using canned oscillators that do not require long start-up times from stop mode. external crystal applicatio ns should use the full stop recovery time, that is, with ssrec cleared in the configuration register 1 (config1). 5.4.3 sim counter and reset states external reset has no effect on the sim counter. (see 5.6.2 stop mode for details.) the sim counter is free-running after all reset states. (see 5.3.2 active resets from internal sources for counter control and internal reset recovery sequences.) 5.5 exception control normal, sequential program execution can be changed in three different ways: interrupts ? maskable hardware cpu interrupts ? non-maskable software interrupt instruction (swi) reset break interrupts 5.5.1 interrupts an interrupt temporarily changes the sequence of pr ogram execution to respond to a particular event. figure 5-8 flow charts the handling of system interrupts. interrupts are latched, and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which vector to fetch. once an interrupt is latched by the sim, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the i bit is cleared). system integration module (sim) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 68 freescale semiconductor figure 5-8. interrupt processing no no no yes no no yes no yes yes (as many interrupts as exist on chip) i bit set? from reset break interrupt? i bit set? irq interrupt? timer 1 interrupt? swi instruction? rti instruction? fetch next instruction unstack cpu registers. stack cpu registers. set i bit. load pc with interrupt vector. execute instruction. yes yes exception control mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 69 at the beginning of an interrupt, the cpu saves the cpu register contents on the stack and sets the interrupt mask (i bit) to prevent additional interrupts. at the end of an interrupt, the rti instruction recovers the cpu register contents from the stack so that normal processing can resume. figure 5-9 shows interrupt entry timing. figure 5-10 shows interrupt recovery timing. figure 5-9 . interrupt entry figure 5-10. interrupt recovery 5.5.1.1 hardware interrupts a hardware interrupt does not stop the current instruction. processing of a hardware interrupt begins after completion of the current instruction. when the current instruction is complete, the sim checks all pending hardware interrupts. if interrupts are not masked (i bit clear in the condition code register), and if the corresponding interrupt enable bit is set, the sim proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. if more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. figure 5-11 demonstrates what happens when two in terrupts are pending. if an interrupt is pending upon exit from the original interrupt servic e routine, the pending interrupt is serviced before the lda instruction is executed. module idb r/w interrupt dummy sp sp ? 1 sp ? 2 sp ? 3 sp ? 4 vect h vect l start addr iab dummy pc ? 1[7:0] pc ? 1[15:8] x a ccr v data h v data l opcode i bit module idb r/w interrupt sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp pc pc + 1 iab ccr a x pc ? 1[15:8] pc ? 1[7:0] opcode operand i bit system integration module (sim) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 70 freescale semiconductor figure 5-11 . interrupt recognition example the lda opcode is prefetched by both the int1 and int2 rti instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. note to maintain compatibility with the m6805 family, the h register is not pushed on the stack during interrupt entry. if the interrupt service routine modifies the h register or uses the indexed addressing mode, software should save the h register and then restore it prior to exiting the routine. 5.5.1.2 swi instruction the swi instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (i bit) in the condition code register. note a software interrupt pushes pc onto the stack. a software interrupt does not push pc ? 1, as a hardware interrupt does. 5.5.2 interrupt status registers the flags in the interrupt status registers identify maskable interrupt sources. table 5-3 summarizes the interrupt sources and the interrupt status register flags that they set. the interrupt status registers can be useful for debugging. cli lda int1 pulh rti int2 background routine #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine exception control mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 71 5.5.2.1 interrupt status register 1 if1, if3 to if6 ? interrupt flags these flags indicate the presence of interrupt requests from the sources shown in table 5-3 . 1 = interrupt request present 0 = no interrupt request present bit 0, 1, and 3 ? always read 0 table 5-3. interrupt sources priority source flag mask (1) int flag vector address highest reset ? ? ? $fffe?$ffff swi instruction ? ? ? $fffc?$fffd irq pin irqf imask if1 $fffa?$fffb timer 1 channel 0 interrupt ch0f ch0ie if3 $fff6?$fff7 timer 1 channel 1 interrupt ch1f ch1ie if4 $fff4?$fff5 timer 1 overflow interrupt tof toie if5 $fff2?$fff3 timer 2 channel 0 interrupt ch0f ch0ie if6 $fff0?$fff1 timer 2 channel 1 interrupt ch1f ch1ie if7 $ffee?$ffef timer 2 overflow interrupt tof toie if8 $ffec?$ffed sci error or nf fe pe orie neie feie peie if11 $ffe6?$ffe7 sci receive scrf idle scrie ilie if12 $ffe4?$ffe5 sci transmit scte tc sctie tcie if13 $ffe2?$ffe3 keyboard interrupt keyf imaskk if14 $ffe0?$ffe1 lowest adc conversion complete interrupt coco aien if15 $ffde?$ffdf 1. the i bit in the condition code register is a global mask for all interrupts source s except the swi instruction. address: $fe04 bit 7654321bit 0 read: if6 if5 if4 if3 0 if1 0 0 write:rrrrrrrr reset:00000000 r= reserved figure 5-12. interrupt status register 1 (int1) system integration module (sim) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 72 freescale semiconductor 5.5.2.2 interrupt status register 2 if7, if8, if11 to f14 ? interrupt flags this flag indicates the presence of interr upt requests from the sources shown in table 5-3 . 1 = interrupt request present 0 = no interrupt request present bit 2 and 3 ? always read 0 5.5.2.3 interrupt status register 3 if15 ? interrupt flags these flags indicate the presence of interrupt requests from the sources shown in table 5-3 . 1 = interrupt request present 0 = no interrupt request present bit 1 to 7 ? always read 0 5.5.3 reset all reset sources always have equal and highest priority and cannot be arbitrated. 5.5.4 break interrupts the break module can stop normal program flow at a software-programmable break point by asserting its break interrupt output. (see chapter 16 break module (break) .) the sim puts the cpu into the break state by forcing it to the swi vector location. refer to the break interrupt subsection of each module to see how each module is affected by the break state. address: $fe05 bit 7654321bit 0 read: if14 if13 if12 if11 0 0 if8 if7 write:rrrrrrrr reset:00000000 r= reserved figure 5-13. interrupt status register 2 (int2) address: $fe06 bit 7654321bit 0 read:0000000if15 write:rrrrrrrr reset:00000000 r= reserved figure 5-14. interrupt status register 3 (int3) low-power modes mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 73 5.5.5 status flag pr otection in break mode the sim controls whether status flags contained in other modules can be cleared during break mode. the user can select whether flags are protected from bei ng cleared by properly initializing the break clear flag enable bit (bcfe) in the break flag control register (bfcr). protecting flags in break mode ensures that set fl ags will not be cleared while in break mode. this protection allows registers to be freely read and writ ten during break mode without losing status flag information. setting the bcfe bit enables the clearing mechani sms. once cleared in break mode, a flag remains cleared even when break mode is exited. status flags with a two-step clearing mechanism ? for example, a read of one register followed by the read or write of another ? are protected, even when the first step is accomplished prior to entering break mode. upon leaving break mode, execution of the second step will clear the flag as normal. 5.6 low-power modes executing the wait or stop instruction puts the mcu in a low-power-consumption mode for standby situations. the sim holds the cpu in a non-clocked st ate. the operation of each of these modes is described below. both stop and wait clear the interrupt mask (i) in the condition code register, allowing interrupts to occur. 5.6.1 wait mode in wait mode, the cpu clocks are inactive wh ile the peripheral clocks continue to run. figure 5-15 shows the timing for wait mode entry. a module that is active during wait mode can wake up the cpu with an interrupt if the interrupt is enabled. stacking for the interrupt begins one cycle after the wa it instruction during which the interrupt occurred. in wait mode, the cpu clocks are inactive. refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. wait mode can also be exited by a reset or break. a break interrupt during wait mode sets the sim break stop/wait bit, sbsw, in the break status register (bsr ). if the cop disable bit, copd, in the mask option register is logic zero, then the computer operatin g properly module (cop) is enabled and remains active in wait mode. figure 5-15. wait mode entry timing figure 5-16 and figure 5-17 show the timing for wait recovery. wait addr + 1 same same iab idb previous data next opcode same wait addr same r/w note: previous data can be operand data or the wait opcode, depending on the last instruction. system integration module (sim) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 74 freescale semiconductor figure 5-16. wait recovery from interrupt or break figure 5-17. wait recovery from internal reset 5.6.2 stop mode in stop mode, the sim counter is reset and the system clocks are disabled. an interrupt request from a module can cause an exit from stop mode. stacking for interrupts begins after the selected stop recovery time has elapsed. reset or break also causes an exit from stop mode. the sim disables the oscillator signals (oscout) in stop mode, stopping the cpu and peripherals. stop recovery time is selectable using the ssrec bit in the configuration register 1 (config1). if ssrec is set, stop recovery is reduced from the normal delay of 4096 iclk cycles down to 32. this is ideal for applications using canned oscillators that do not require long start-up times from stop mode. note external crystal applications should use the full stop recovery time by clearing the ssrec bit. a break interrupt during stop mode sets the sim break stop/wait bit (sbsw) in the break status register (bsr). the sim counter is held in reset from the execution of the stop instruction until the beginning of stop recovery. it is then used to time the recovery period. figure 5-18 shows stop mode entry timing. note to minimize stop current, all pins conf igured as inputs should be driven to a logic 1 or logic 0. $6e0c $6e0b $00ff $00fe $00fd $00fc $a6 $a6 $01 $0b $6e $a6 iab idb exitstopwait note: exitstopwait = rst pin or cpu interrupt or break interrupt iab idb rst $a6 $a6 $6e0b rst vct h rst vct l $a6 iclk 32 cycles 32 cycles sim registers mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 75 figure 5-18. stop mode entry timing figure 5-19. stop mode recovery from interrupt or break 5.7 sim registers the sim has three memory mapped registers. break status register (bsr) reset status register (rsr) break flag control register (bfcr) 5.7.1 break status register (bsr) the break status register contains a flag to indicate that a break caused an exit from stop or wait mode. address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note (1) reset:00000000 r = reserved 1. writing a logic zero clears sbsw. figure 5-20. break status register (bsr) stop addr + 1 same same iab idb previous data next opcode same stop addr same r/w cpustop note: previous data can be operand data or the stop opcode, depending on the last instruction. iclk int/break iab stop + 2 stop + 2 sp sp ? 1 sp ? 2 sp ? 3 stop +1 stop recovery period system integration module (sim) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 76 freescale semiconductor sbsw ? sim break stop/wait this status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. clear sbsw by writing a l ogic zero to it. reset clears sbsw. 1 = stop mode or wait mode was exited by break interrupt 0 = stop mode or wait mode was not exited by break interrupt sbsw can be read within the break state swi routine. the user can modify t he return address on the stack by subtracting one from it. th e following code is an example of this. writing zero to the sbsw bit clears it. 5.7.2 reset stat us register (rsr) this register contains six flags that show the source of the last reset. clear the sim reset status register by reading it. a power-on reset sets the por bi t and clears all other bits in the register. por ? power-on reset bit 1 = last reset caused by por circuit 0 = read of rsr ; ; ; this code works if the h register has been pushed onto the stack in the break service routine software. this code should be executed at the end of the break service routine software. hibyte equ 5 lobyte equ 6 ; if not sbsw, do rti brclr sbsw,bsr, return ; ; see if wait mode or stop mode was exited by break. tst lobyte,sp ; if returnlo is not zero, bne dolo ; then just decrement low byte. dec hibyte,sp ; else deal with high byte, too. dolo dec lobyte,sp ; point to wait/stop opcode. return pulh rti ; restore h register. address: $fe01 bit 7654321bit 0 read: por pin cop ilop ilad modrst lvi 0 write: por:10000000 = unimplemented figure 5-21. reset status register (rsr) sim registers mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 77 pin ? external reset bit 1 = last reset caused by external reset pin (rst ) 0 = por or read of rsr cop ? computer operating properly reset bit 1 = last reset caused by cop counter 0 = por or read of rsr ilop ? illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of rsr ilad ? illegal address reset bit (opcode fetches only) 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of rsr modrst ? monitor mode entry module reset bit 1 = last reset caused by monitor mode entry when vector locations $fffe and $ffff are $ff after por while irq = v dd 0 = por or read of rsr lvi ? low voltage inhibit reset bit 1 = last reset caused by lvi circuit 0 = por or read of rsr 5.7.3 break flag cont rol register (bfcr) the break control register contains a bit that enables software to clear status bits while the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bi ts by accessing status r egisters while the mcu is in a break state. to clear status bits duri ng the break state, the bcfe bit must be set. 1 = status bits cl earable during break 0 = status bits not clearable during break address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r= reserved figure 5-22. break flag control register (bfcr) system integration module (sim) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 78 freescale semiconductor mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 79 chapter 6 oscillator (osc) 6.1 introduction the oscillator module provides the reference cloc ks for the mcu system and bus. two oscillators are running on the device: selectable oscillat or ? for bus clock crystal oscillator (xtal) ? built-in oscillator that requires an external crystal or ceramic-resonator. this option also allows an external clock that can be driven directly into osc1. rc oscillator (rc) ? built-in oscillator that re quires an external resistor-capacitor connection only. the selected oscillator is used to drive the bus clock, the sim, and other modules on the mcu. the oscillator type is selected by programming a bit fl ash memory. the rc and crystal oscillator cannot run concurrently; one is disabled while the other is se lected; because the rc and xtal circuits share the same osc1 pin. non-selectable oscill ator ? for cop internal oscillator ? built-in rc oscillator that requires no external components. this internal oscillator is used to drive the comp uter operating properly (cop) module and the sim. the internal oscillator runs continuously afte r a por or reset, and is always available. 6.2 oscillator selection the oscillator type is selected by programming a bit in a flash memory location; the mask option register (mor), at $ffd0. (see 3.5 mask option register (mor) .) note on the rom device, the oscillator is selected by a rom-mask layer at factory. address: $ffd0 bit 7654321bit 0 read: oscselrrrrrrr write: erased:11111111 reset: unaffected by reset non-volatile flash register; write by programming. r=reserved figure 6-1. mask option register (mor) oscillator (osc) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 80 freescale semiconductor oscsel ? oscillator select bit oscsel selects the oscillator type for the mcu. the erased or unprogrammed state of this bit is logic 1, selecting the crystal oscillator option. this bit is unaffected by reset. 1 = crystal oscillator 0 = rc oscillator bits 6?0 ? should be left as logic 1?s. note when crystal oscillator is selected, the osc2/rcclk/pta6/kbi6 pin is used as osc2; other functions such as pta6/kbi6 will not be available. 6.2.1 xtal oscillator the xtal oscillator circuit is designed for use with an external crystal or ceramic resonator to provide accurate clock source. in its typical configuration, the xtal oscillator is conn ected in a pierce oscillator configuration, as shown in figure 6-2 . this figure shows only the logical representation of the internal components and may not represent actual circuitry. the oscillat or configuration us es five components: crystal, x 1 fixed capacitor, c 1 tuning capacitor, c 2 (can also be a fixed capacitor) feedback resistor, r b series resistor, r s (optional) figure 6-2. xtal oscillator external connections the series resistor (r s ) is included in the diagram to follow strict pierce oscillator guidelines and may not be required for all ranges of operation, especially with high frequency crystals. refer to the crystal manufacturer?s data for more information. c 1 c 2 simoscen xtalclk r b x 1 r s * *r s can be zero (shorted) when used with higher-frequency crystals. mcu from sim refer to manufacturer?s data. osc2 osc1 2 oscout 2oscout to sim to sim see chapter 17 for component value requirements. internal oscillator mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 81 6.2.2 rc oscillator the rc oscillator circuit is designed for use with exte rnal resistor and capacitor to provide a clock source with tolerance less than 10%. in its typical configuration, the rc oscillator requires two external components, one r and one c. component values should have a tolerance of 1% or less, to obtain a clock source with less than 10% tolerance. the oscillator configuration uses two components: c ext r ext figure 6-3. rc oscillator external connections 6.3 internal oscillator the internal oscillator clock (iclk) is a free runn ing 50-khz clock that requi res no external components. it is used as the reference clock input to the co mputer operating properly (cop) module and the sim. the internal oscillator by default is always availa ble and is free running after por or reset. it can be stopped in stop mode by setting the stop_iclkdis bit before executing the stop instruction. figure 6-4 shows the logical representation of compone nts of the internal oscillator circuitry. figure 6-4. internal oscillator mcu r ext c ext simoscen osc1 ext-rc oscillator en rcclk 2 oscout 2oscout to sim from sim v dd pta6 i/o 0 1 pta6 pta6en rcclk/pta6 (osc2) to sim see chapter 17 for component value requirements. internal en simoscen stop_iclkdis config2 iclk from sim to sim and cop oscillator oscillator (osc) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 82 freescale semiconductor note the internal oscillator is a free runni ng oscillator and is available after each por or reset. it is turned-off in stop mode by setting the stop_iclkdis bit in config2 (see 3.4 configuration register 2 (config2) ) . 6.4 i/o signals the following paragraphs descri be the oscillator i/o signals. 6.4.1 crystal amplifi er input pin (osc1) osc1 pin is an input to the crystal oscillator amplifier or the input to the rc oscillator circuit. 6.4.2 crystal amplifier out put pin (osc2/rcclk/pta6/kbi6) for the xtal oscillator , osc2 pin is the output of the crystal oscillator inverting amplifier. for the rc oscillator, osc2 pin can be configured as a general purpose i/o pin pta6, or the output of the rc oscillator, rcclk. 6.4.3 oscillator e nable signal (simoscen) the simoscen signal comes from the system integration module (sim) and enables/disables the xtal oscillator circuit or the rc-oscillator. 6.4.4 xtal oscillator clock (xtalclk) xtalclk is the xtal oscillator output signal. it runs at the full speed of the crystal (f xclk ) and comes directly from the crystal oscillator circuit. figure 6-2 shows only the logical relation of xtalclk to osc1 and osc2 and may not represent the actual circui try. the duty cycle of xtalclk is unknown and may depend on the crystal and other external factors. al so, the frequency and amplitude of xtalclk can be unstable at start-up. 6.4.5 rc oscillat or clock (rcclk) rcclk is the rc oscillator output signal. its frequency is directly proportional to the time constant of the external r and c. figure 6-3 shows only the logical relation of rcclk to osc1 and may not represent the actual circuitry. 6.4.6 oscillator out 2 (2oscout) 2oscout is same as the input clock (xtalclk or rcclk). this signal is dr iven to the sim module. oscillator osc2 pin function xtal inverting osc1 rc controlled by pta6en bit in ptapue ($000d) pta6en = 0: rcclk output pta6en = 1: pta6/kbi6 low power modes mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 83 6.4.7 oscillat or out (oscout) the frequency of this signal is equal to half of the 2oscout, this signal is driven to the sim for generation of the bus clocks used by the cpu and other modules on the mcu. oscout will be divided again in the sim and results in the internal bus frequency being one fourth of the xtalclk or rcclk frequency. 6.4.8 internal oscillator clock (iclk) iclk is the internal oscillator output signal (typic ally 50-khz), for the cop module and the sim. its frequency depends on the v dd voltage. (see chapter 17 electrical specifications for iclk parameters.) 6.5 low power modes the wait and stop instructions put the mcu in low-power consumption standby modes. 6.5.1 wait mode the wait instruction has no effect on the oscillat or logic. oscout, 2oscout, and iclk continues to drive to the sim module. 6.5.2 stop mode the stop instruction disables the xtalclk or the rcclk output, hence, oscout and 2oscout are disabled. the stop instruction also turns off the iclk input to the cop module if the stop_iclkdis bit is set in configuration register 2 (config2). after reset, t he stop_iclkdis bit is clear by default and iclk is enabled during stop mode. 6.6 oscillator during break mode the oscout, 2oscout, and iclk cloc ks continue to be driven out when the device enters the break state. oscillator (osc) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 84 freescale semiconductor mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 85 chapter 7 monitor rom (mon) 7.1 introduction this section describes the moni tor rom (mon) and the monitor mode entry methods. the monitor rom allows complete testing of the mcu through a single- wire interface with a host computer. this mode is also used for programming and erasing of flash me mory in the mcu. monitor mode entry can be achieved without use of the higher test voltage, v tst , as long as vector addresses $fffe and $ffff are blank, thus reducing the hardware r equirements for in-circuit programming. 7.2 features features of the monitor rom include the following: normal user-mode pin functionality one pin dedicated to serial communicati on between monitor rom and host computer standard mark/space non-return-to-zero (nrz) communication with host computer execution of code in ram or flash flash memory security feature (1) flash memory programming interface 959 bytes monitor rom code size monitor mode entry without high voltage, v tst , if reset vector is blank ($fffe and $ffff contain $ff) standard monitor mode entry if high voltage, v tst , is applied to irq resident routines for flash programming and eeprom emulation 7.3 functional description the monitor rom receives and executes commands from a host computer. figure 7-1 shows a example circuit used to enter monitor mode and communic ate with a host computer via a standard rs-232 interface. simple monitor commands can access any memory address. in monitor mode, the mcu can execute host-computer code in ram while most mcu pins retain normal operating mode functions. all communication between the host computer and the mcu is through the ptb0 pin. a level-shifting and multiplexing interface is required between ptb0 and the host computer. ptb0 is used in a wired-or configuration and requires a pull-up resistor. 1. no security feature is absolutely secure . however, motorola?s strategy is to make reading or copying the flash difficult for unauthorized users. monitor rom (mon) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 86 freescale semiconductor figure 7-1. monitor mode circuit notes: 1. monitor mode entry method: sw1: position a ? high voltage entry (v tst ) bus clock depends on sw2. sw1: position b ? reset vector must be blank ($fffe = $ffff = $ff) bus clock = osc1 4. 2. affects high voltage entry to monitor mode only (sw1 at position a): sw2: position c ? bus clock = osc1 4 sw2: position d ? bus clock = osc1 2 5. see table 17-4 for v tst voltage level requirements. 10m hc908jl8 rst irq osc1 osc2 v ss ptb0 20 pf 20 pf 0.1 f 9.8304mhz ptb1 v dd 0.1 f v dd ptb2 v dd 10 k ptb3 v dd 10 k 10 k sw2 c d v dd (see note 2) a b xtal circuit 16 15 2 6 v dd max232 v+ v? v dd 10 k c1+ c1? 5 4 c2+ c2? + 3 1 1 f + + + 8 7 db9 2 3 5 10 9 + 1 2 3 4 5 6 74hc125 74hc125 1 k v tst v cc gnd 1 f 1 f 1 f 1 f 8.5 v v dd 10 k 10 k ext osc (50% duty) ext osc connection to osc1, with osc2 unconnected, can replace xtal circuit. osc1 (see note 1) sw1 functional description mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 87 7.3.1 entering monitor mode table 7-1 shows the pin conditions for entering monitor m ode. as specified in the table, monitor mode may be entered after a por. communication at 9600 baud will be established provided one of the following sets of conditions is met: 1. if irq = v tst : ? clock on osc1 is 4.9125mhz ?ptb3 = low 2. if irq = v tst : ? clock on osc1 is 9.8304mhz ? ptb3 = high 3. if $fffe and $ffff are blank (contain $ff): ? clock on osc1 is 9.8304mhz ?irq = v dd if v tst is applied to irq and ptb3 is low upon monitor mode entry ( table 7-1 condition set 1), the bus frequency is a divide-by-two of the clock input to osc1. if ptb3 is high with v tst applied to irq upon monitor mode entry ( table 7-1 condition set 2), the bus frequency is a divide-by-four of the clock input to osc1. holding the ptb3 pin low when entering moni tor mode causes a bypass of a divide-by-two stage at the oscillator only if v tst is applied to irq . in this event, the oscout frequency is equal to the 2oscout frequency, and osc1 input directly generates internal bus clocks. in this case, the osc1 signal must have a 50% duty cycle at maximum bus frequency. entering monitor mode with v tst on irq , the cop is disabled as long as v tst is applied to either irq or rst . (see chapter 5 system integration module (sim) for more information on modes of operation.) if entering monitor mode without high voltage on irq and reset vector being blank ($fffe and $ffff) ( table 7-1 condition set 3, where applied voltage is v dd ), then all port b pin requirements and conditions, table 7-1. monitor mode entry requirements and options irq $fffe and $ffff ptb3 ptb2 ptb1 ptb0 osc1 clock (1) 1. rc oscillator cannot be used for monitor mode; must us e either external oscillator or xtal oscillator circuit. bus frequency comments v tst (2) 2. see table 17-4 for v tst voltage level requirements. x 0011 4.9152mhz 2.4576mhz high voltage entry to monitor mode. 9600 baud communication on ptb0. cop disabled. v tst (1) x 1011 9.8304mhz 2.4576mhz v dd blank (contain $ff) x x x 1 9.8304mhz 2.4576mhz blank reset vector (low-voltage) entry to monitor mode. 9600 baud communication on ptb0. cop disabled. v dd not blank xxxx x osc1 4 enters user mode. monitor rom (mon) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 88 freescale semiconductor including the ptb3 frequency divisor selection, are not in effect. this is to reduce circuit requirements when performing in-circuit programming. entering monitor mode with the reset vector being blan k, the cop is always disabled regardless of the state of irq or the rst . figure 7-2 . shows a simplified diagram of the monitor mode entry when the reset vector is blank and irq = v dd . an osc1 frequency of 9.8304mhz is required for a baud rate of 9600. figure 7-2. low-voltage monitor mode entry flowchart enter monitor mode with the pin conf iguration shown above by pulling rst low and then high. the rising edge of rst latches monitor mode. once monitor mode is latched, the values on the specified pins can change. once out of reset, the mcu waits for the host to send eight security bytes. (see 7.4 security .) after the security bytes, the mcu sends a break signal (10 consec utive logic zeros) to the host, indicating that it is ready to receive a command. the break signal also provides a timing reference to allow the host to determine the necessary baud rate. in monitor mode, the mcu uses different vectors for reset, swi, and break interrupt. the alternate vectors are in the $fe page instead of the $ff page and allow code execution from the internal monitor firmware instead of user code. table 7-2 is a summary of the vector differenc es between user mode and monitor mode. is vector blank? por triggered? normal user mode monitor mode execute monitor code no no yes yes por reset functional description mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 89 when the host computer has completed downloading code into the mcu ram, the host then sends a run command, which executes an rti, which sends control to the address on the stack pointer. 7.3.2 baud rate the communication baud rate is dependant on oscillator frequency. the state of ptb3 also affects baud rate if entry to monitor mode is by irq =v tst . when ptb3 is high, the divide by ratio is 1024. if the ptb3 pin is at logic zero upon entry into mo nitor mode, the divide by ratio is 512. 7.3.3 data format communication with the monitor rom is in standard non-return-to-zero (nrz) ma rk/space data format. (see figure 7-3 and figure 7-4 .) figure 7-3. monitor data format figure 7-4. sample monitor waveforms table 7-2. monitor mode vector differences modes functions cop reset vector high reset vector low break vector high break vector low swi vector high swi vector low user enabled $fffe $ffff $fffc $fffd $fffc $fffd monitor disabled (1) $fefe $feff $fefc $fefd $fefc $fefd notes: 1. if the high voltage (v tst ) is removed from the irq pin or the rst pin, the sim asserts its cop enable output. the cop is a mask op tion enabled or disabled by the copd bit in the configuration register. table 7-3. monitor baud rate selection monitor mode entry by: osc1 clock frequency ptb3 baud rate irq = v tst 4.9152 mhz 0 9600 bps 9.8304 mhz 1 9600 bps 4.9152 mhz 1 4800 bps blank reset vector, irq = v dd 9.8304 mhz x 9600 bps 4.9152 mhz x 4800 bps bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 start bit bit 0 bit 1 next stop bit start bit bit 2 $a5 break bit 3 bit 4 bit 5 bit 6 bit 7 monitor rom (mon) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 90 freescale semiconductor the data transmit and receive rate can be anywhere from 4800 baud to 28.8k-baud. transmit and receive baud rates must be identical. 7.3.4 echoing as shown in figure 7-5 , the monitor rom immediately echoes eac h received byte back to the ptb0 pin for error checking. figure 7-5. read transaction any result of a command appears after the echo of the last byte of the command. 7.3.5 break signal a start bit followed by nine lo w bits is a break signal. (see figure 7-6 .) when the monitor receives a break signal, it drives the ptb0 pin high for the duration of two bits before echoing the break signal. figure 7-6. break transaction 7.3.6 commands the monitor rom uses the following commands: read (read memory) write (write memory) iread (indexed read) iwrite (indexed write) readsp (read stack pointer) run (run user program) addr. high read read addr. high addr. low addr. low data echo sent to monitor result 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 missing stop bit two-stop-bit delay before zero echo functional description mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 91 table 7-4. read (read memory) command description read byte from memory operand specifies 2-byte address in high byte:low byte order data returned returns contents of specified address opcode $4a command sequence table 7-5. write (write memory) command description write byte to memory operand specifies 2-byte address in high byte:low byte order; low byte followed by data byte data returned none opcode $49 command sequence addr. high read read addr. high addr. low addr. low data echo sent to monitor result addr. high write write addr. high addr. low addr. low data echo sent to monitor data monitor rom (mon) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 92 freescale semiconductor note a sequence of iread or iwrite co mmands can sequentially access a block of memory over the full 64-kbyte memory map. table 7-6. iread (indexed read) command description read next 2 bytes in me mory from last address accessed operand specifies 2-byte address in high byte:low byte order data returned returns contents of next two addresses opcode $1a command sequence table 7-7. iwrite (indexed write) command description write to last address accessed + 1 operand specifies single data byte data returned none opcode $19 command sequence data iread iread data echo sent to monitor result data iwrite iwrite data echo sent to monitor security mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 93 7.4 security a security feature discourages unauthorized reading of flash locations while in monitor mode. the host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $fff6?$fffd. locations $fff6?$fffd contain user-defined data. note do not leave locations $fff6?$fffd bl ank. for security reasons, program locations $fff6?$fffd even if they are not used for vectors. during monitor mode entry, the mcu waits after the powe r-on reset for the host to send the eight security bytes on pin ptb0. if the received bytes match those at locations $fff6?$fffd, the host bypasses the security feature and can read all flash locations and execute code from flash. security remains bypassed until a power-on reset occurs. if the reset wa s not a power-on reset, security remains bypassed and security code entry is not required. (see figure 7-7 .) table 7-8. readsp (read stack pointer) command description reads stack pointer operand none data returned returns stack pointer in high byte:low byte order opcode $0c command sequence table 7-9. run (run user program) command description executes rti instruction operand none data returned none opcode $28 command sequence sp high readsp readsp sp low echo sent to monitor result run run echo sent to monitor monitor rom (mon) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 94 freescale semiconductor figure 7-7. monitor mode entry timing upon power-on reset, if the received bytes of the security code do not match the data at locations $fff6?$fffd, the host fails to bypass the security feature. the mcu remains in monitor mode, but reading a flash location returns an invalid value and trying to execute code from flash causes an illegal address reset. after receiving the eight secu rity bytes from the host, the mcu transmits a break character, signifying that it is ready to receive a command. note the mcu does not transmit a break char acter until after the host sends the eight security bytes. to determine whether the security code entered is correct, check to see if bit 6 of ram address $60 is set. if it is, then the correct security code has been entered and flash can be accessed. if the security sequence fails, the device should be reset by a power-on reset and brought up in monitor mode to attempt another entry. after failing the securi ty sequence, the flash module can also be mass erased by executing an erase routine that was downl oaded into internal ram. the mass erase operation clears the security code locations so that all eight security bytes become $ff (blank). 7.5 rom-resident routines eight routines stored in the monitor rom area (t hus rom-resident) are provided for flash memory manipulation. six of the eight routines are int ended to simplify flash program, erase, and load operations. the other two routines are intended to simplify t he use of the flash memory as eeprom. table 7-10 shows a summary of the rom-resident routines. byte 1 byte 1 echo byte 2 byte 2 echo byte 8 byte 8 echo command command echo ptb0 rst v dd 4096 + 32 iclk cycles 24 bus cycles 141 12 1 break notes: 2 = data return delay, 2 bit times 4 = wait 1 bit time before sending next byte. 4 from host from mcu 1 = echo delay, 2 bit times rom-resident routines mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 95 the routines are designed to be called as stand-alone subroutines in the user program or monitor mode. the parameters that are passed to a routine are in the form of a contiguous data block, stored in ram. the index register (h:x) is loaded with the address of the first byte of the data block (acting as a pointer), and the subroutine is called (jsr). using the start addr ess as a pointer, multiple data blocks can be used, any area of ram be used. a data block has the control and data bytes in a defined order, as shown in figure 7-8 . during the software execution, it does not consume any dedicated ram location, the run-time heap will extend the system stack, all other ram location will not be affected. figure 7-8. data block format for rom-resident routines table 7-10. summary of rom-resident routines routine name routine description call address stack used (1) (bytes) prgrnge program a range of locations $fc06 15 erarnge erase a page or the entire array $fcbe 9 ldrnge loads data from a range of locations $ff30 9 mon_prgrnge program a range of locations in monitor mode $ff28 17 mon_erarnge erase a page or the entire array in monitor mode $ff2c 11 mon_ldrnge loads data from a range of locations in monitor mode $ff24 11 ee_write emulated eeprom write. data size ranges from 2 to 15 bytes at a time. $fd3f 24 ee_read emulated eeprom read. data size ranges from 2 to 15 bytes at a time. $fdd0 16 1. the listed stack size excludes the 2 by tes used by the calling instruction, jsr. data size (datasize) start address high (addrh) start address low (addrl) data 0 data 1 bus speed (bus_spd) file_ptr data n data array $xxxx data block address as pointer ram monitor rom (mon) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 96 freescale semiconductor the control and data bytes are described below. bus speed ? this one byte indicates the operating bus speed of the mcu. the value of this byte should be equal to 4 times the bus speed, and shou ld not be set to less than 4 (i.e. minimum bus speed is 1mhz). data size ? this one byte indicates the number of bytes in the data array that are to be manipulated. the maximum data array size is 128. routines ee_write and ee_read are restricted to manipulate a data array between 2 to 15 bytes. whereas routines erarnge and mon_erarnge do not manipulate a data array, thus, this data size byte has no meaning. start address ? these two bytes, high byte followed by low byte, indicate the start address of the flash memory to be manipulated. data array ? this data array contains data that are to be manipulated. data in this array are programmed to flash memory by the progr amming routines: prgrnge, mon_prgrnge, ee_write. for the read routines: ldrnge, mo n_ldrnge, and ee_read, data is read from flash and stored in this array. 7.5.1 prgrnge prgrnge is used to program a range of flash locations with data loaded into the data array. the start location of the flash to be programmed is specified by the a ddress addrh:addrl and the number of bytes from this location is specified by datasize. the maximum number of bytes that can be programmed in one routine call is 1 28 bytes (max. datasize is 128). addrh:addrl do not need to be at a page boundary, the routine handles any boundary misalignment during programming. a check to see that all bytes in the specified range are erased is not performed by this routine prior programming. nor does this routine do a verification after programming, so there is no return confirmation that programming was successful. user must assure that the range specified is first erased. the coding example below is to program 32 bytes of data starting at flash location $ef00, with a bus speed of 4.9152 mhz. the coding assumes the data block is already loaded in ram, with the address pointer, file_ptr, pointing to the first byte of the data block. table 7-11. prgrnge routine routine name prgrnge routine description program a range of locations calling address $fc06 stack used 15 bytes data block format bus speed (bus_spd) data size (datasize) start address high (addrh) start address (addrl) data 1 (data1) : data n (datan) rom-resident routines mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 97 org ram : file_ptr: bus_spd ds.b 1; indicates 4x bus frequency datasize ds.b 1; data size to be programmed start_addr ds.w 1; flash start address dataarray ds.b 32; reserved data array prgrnge equ $fc06 flash_start equ $ef00 org flash initialisation: mov #20, bus_spd mov #32, datasize ldhx #flash_start sthx start_addr rts main: bsr initialisation : : ldhx #file_ptr jsr prgrnge 7.5.2 erarnge erarnge is used to erase a range of locations in flash. there are two sizes of erase ranges: a page or t he entire array. the erarnge will erase the page (64 consecutive bytes) in flash s pecified by the address addrh:a ddrl. this address can be any address within the page. calling erarnge with addrh:addrl equal to $ffff will erase the entire flash array (mass erase). therefore, care must be taken when calling this routine to prevent an accidental mass erase. to avoid undesirable routine return addresse s after a mass erase, the erarnge routine should not be called from code executed from flash memory . load the code into an area of ram before calling the erarnge routine. the erarnge routine do not use a data array. the dat asize byte is a dummy by te that is also not used. table 7-12. erarnge routine routine name erarnge routine description erase a page or the entire array calling address $fcbe stack used 9 bytes data block format bus speed (bus_spd) data size (datasize) starting address (addrh) starting address (addrl) monitor rom (mon) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 98 freescale semiconductor the coding example below is to perform a page erase, from $ef00?$ef3f. the initialization subroutine is the same as the coding example for prgrnge (see 7.5.1 prgrnge ). erarnge equ $fcbe main: bsr initialisation : : ldhx #file_ptr jsr erarnge : 7.5.3 ldrnge ldrnge is used to load the data array in ram with data from a range of flash locations. the start location of flash from where data is re trieved is specified by the address addrh:addrl and the number of bytes from this location is specified by datasize. the maximum number of bytes that can be retrieved in one routine call is 128 bytes. the data retrieved from flash is loaded into the data array in ram. previous data in the data array will be overwr itten. user can use this routine to retrieve data from flash that was previously programmed. the coding example below is to retrieve 32 bytes of data starting from $ef00 in flash. the initialization subroutine is the same as the coding example for prgrnge (see 7.5.1 prgrnge ). ldrnge equ $ff30 main: bsr initialization : : ldhx #file_ptr jsr ldrnge : table 7-13. ldrnge routine routine name ldrnge routine description loads data from a range of locations calling address $ff30 stack used 9 bytes data block format bus speed (bus_spd) data size (datasize) starting address (addrh) starting address (addrl) data 1 : data n rom-resident routines mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 99 7.5.4 mon_prgrnge in monitor mode, mon_prgrnge is used to program a range of flash locations with data loaded into the data array. the mon_prgrnge routine is designed to be used in monitor mode. it performs the same function as the prgrnge routine (see 7.5.1 prgrnge ), except that mon_prgrnge returns to the main program via an swi instruction. after a mon_prgrnge call, th e swi instruction will return the control back to the monitor code. 7.5.5 mon_erarnge in monitor mode, erarnge is used to erase a range of locations in flash. the mon_erarnge routine is designed to be used in monitor mode. it performs the same function as the erarnge routine (see 7.5.2 erarnge ), except that mon_erarnge returns to the main program via an swi instruction. after a mon_erarnge call, the swi instruction will return the control back to the monitor code. table 7-14. mon_prgrnge routine routine name mon_prgrnge routine description program a range of locations, in monitor mode calling address $fc28 stack used 17 bytes data block format bus speed data size starting address (high byte) starting address (low byte) data 1 : data n table 7-15. mon_erarnge routine routine name mon_erarnge routine description erase a page or the entire array, in monitor mode calling address $ff2c stack used 11 bytes data block format bus speed data size starting address (high byte) starting address (low byte) monitor rom (mon) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 100 freescale semiconductor 7.5.6 mon_ldrnge in monitor mode, ldrnge is used to load the data array in ram with data from a range of flash locations. the mon_ldrnge routine is designed to be used in m onitor mode. it performs the same function as the ldrnge routine (see 7.5.3 ldrnge ), except that mon_ldrnge returns to the main program via an swi instruction. after a mon_ldrnge call, the swi instruction will return the control back to the monitor code. 7.5.7 ee_write ee_write is used to write a set of data from the data array to flash. the start location of the flash to be programmed is specified by the a ddress addrh:addrl and the number of bytes in the data array is specified by datasize. the minimum number of bytes that can be table 7-16. icp_ldrnge routine routine name mon_ldrnge routine description loads data from a range of locations, in monitor mode calling address $ff24 stack used 11 bytes data block format bus speed data size starting address (high byte) starting address (low byte) data 1 : data n table 7-17. ee_write routine routine name ee_write routine description emulated eeprom write. data size ranges from 2 to 15 bytes at a time. calling address $fd3f stack used 24 bytes data block format bus speed (bus_spd) data size (datasize) (1) starting address (addrh) (2) starting address (addrl) (1) data 1 : data n 1. the minimum data size is 2 bytes. the maximum data size is 15 bytes. 2. the start address must be a page boundary st art address: $xx00, $xx40, $xx80, or $00c0. rom-resident routines mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 101 programmed in one routine call is 2 bytes, the maxi mum is 15 bytes. addrh:addrl must always be the start of boundary address (the page start address: $xx00, $xx40, $xx80, or $00c0) and datasize must be the same size when accessing the same page. in some applications, the user may want to repeatedly store and read a set of data from an area of non-volatile memory. this is easily possible when using an eeprom array. as the write and erase operations can be executed on a byte basis. for fl ash memory, the minimum erase size is the page ? 64 bytes per page for mc68hc908jl8. if the data array size is less than the page size, writing and erasing to the same page cannot fully utilize the page. u nused locations in the page will be wasted. the ee_write routine is designed to emulate the pro perties similar to the eeprom. allowing a more efficient use of the flash page for data storage. when the user dedicates a page of flash for data storage, and the size of the data array defined, each call of the ee_wrtie routine will automatically trans fer the data in the data array (in ram) to the next blank block of locations in the flash page. once a page is filled up, the ee_write routine automatically erases the page, and starts to reuse the page again. in the 64-byte page, an 4-byte control block is used by the routine to monitor the utilization of the page. in effect, only 60 bytes are used for data storage. (see figure 7-9 ). the page control operations are transparent to the user. figure 7-9. ee_write flash memory usage when using this routine to store a 3-byte data array, the flash page can be programmed 20 times before the an erase is required. in effect, the write/erase endurance is increased by 20 times. when a 15-byte data array is used, the write/erase endurance is increased by 5 times. due to the flash page size limitation, the data array is limi ted from 2 bytes to 15 bytes. the coding example below uses the $ef00?$ee3f page for data storage. the data array size is 15 bytes, and the bus speed is 4.9152 mhz. the coding assumes th e data block is already loaded in ram, with the address pointer, file_ptr, pointing to the first byte of the data block. page boundary control: 8 bytes data array data array data array $xx00, $xx40, $xx80, or $xxc0 page boundary one page = 64 bytes flash monitor rom (mon) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 102 freescale semiconductor org ram : file_ptr: bus_spd ds.b 1; indicates 4x bus frequency datasize ds.b 1; data size to be programmed start_addr ds.w 1; flash starting address dataarray ds.b 15; reserved data array ee_write equ $fd3f flash_start equ $ef00 org flash initialisation: mov #20, bus_spd mov #15, datasize ldhx #flash_start sthx start_addr rts main: bsr initialisation : : lhdx #file_ptr jsr ee_write note the ee_write routine is unable to check for incorrect data blocks, such as the flash page boundary address and data size. it is the responsibility of the user to ensure the starting addre ss indicated in the data block is at the flash page boundary and the data size is 2 to 15. if the flash page is already programmed with a data array with a different size, the ee_write call will be ignored. rom-resident routines mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 103 7.5.8 ee_read ee_read is used to load the data array in ram with a set of data from flash. the ee_read routine reads data stored by the ee_write routine. an ee_read call will retrieve the last data written to a flash page and loaded into the data array in ram. same as ee_write, the data size indicated by datasize is 2 to 15, and the start address addrh:addrl must the flash page boundary address. the coding example below uses the data st ored by the ee_write coding example (see 7.5.7 ee_write ). it loads the 15-byte data set stored in the $ef00?$ee7f page to the data array in ram. the initialization subroutine is the same as the coding example for ee_write (see 7.5.7 ee_write ). ee_read equ $fdd0 main: bsr initialization : : ldhx file_ptr jsr ee_read : note the ee_read routine is unable to check for incorrect data blocks, such as the flash page boundary address and data size. it is the responsibility of the user to ensure the starting address indicated in the data block is at the flash page boundary and the data size is 2 to 15. if the flash page is programmed with a data array with a di fferent size, the ee_read call will be ignored. table 7-18. ee_read routine routine name ee_read routine description emulated eeprom read. da ta size ranges from 2 to 15 bytes at a time. calling address $fdd0 stack used 16 bytes data block format bus speed (bus_spd) data size (datasize) starting address (addrh) (1) starting address (addrl) (1) data 1 : data n 1. the start address must be a page boundary st art address: $xx00, $xx40, $xx80, or $00c0. monitor rom (mon) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 104 freescale semiconductor mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 105 chapter 8 timer interface module (tim) 8.1 introduction this section describes the timer interface (tim) modul e. the tim is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. figure 8-1 is a block diagram of the tim. this particular mcu has two timer interfac e modules which are denoted as tim1 and tim2. 8.2 features features of the tim include: two input capture/output compare channels: ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action buffered and unbuffered pulse-width-modulation (pwm) signal generation programmable tim clock input ? 7-frequency internal bus clock prescaler selection ? external clock input on timer 2 (bus frequency 2 maximum) free-running or modulo up-count operation toggle any channel pin on overflow tim counter stop and reset bits 8.3 pin name conventions the text that follows describes both timers, tim1 and tim2. the tim input/output (i/o) pin names are t[1,2]ch0 (timer channel 0) and t[1,2]ch1 (timer channel 1), where ?1? is used to indicate tim1 and ?2? is used to indicate tim2. the two tims share four i/o pins with four i/o port pins. the external clock input for tim2 is shared with the an adc channel pin. the full names of the tim i/o pins are listed in table 8-1 . the generic pin names appear in the text that follows. note references to either timer 1 or timer 2 may be made in the following text by omitting the timer number. for example, tch0 may refer generically to t1ch0 and t2ch0, and tch1 ma y refer to t1ch1 and t2ch1. table 8-1. pin name conventions tim generic pin names: t[1,2]ch0 t[1,2]ch1 t2clk full tim pin names: tim1 ptd4/t1ch0 ptd5/t1ch1 ? tim2 pte0/t2ch0 pte1 /t2ch1 adc12/t2clk timer interface module (tim) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 106 freescale semiconductor 8.4 functional description figure 8-1 shows the structure of the tim. the central component of the tim is the 16-bit tim counter that can operate as a free-running counter or a mo dulo up-counter. the tim counter provides the timing reference for the input capture and output compare functions. the tim counter modulo registers, tmodh:tmodl, control the modulo value of the tim counter. software can read the tim counter value at any time without affecting the counting sequence. the two tim channels (per timer) are programmable independently as input capture or output compare channels. figure 8-1. tim block diagram figure 8-2 summarizes the timer registers. note references to either timer 1 or timer 2 may be made in the following text by omitting the timer number. for example, tsc may generically refer to both t1sc and t2sc. prescaler prescaler select internal 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tch0h:tch0l tof toie 16-bit comparator 16-bit latch tch1h:tch1l channel 0 channel 1 tmodh:tmodl trst tstop tov0 ch0ie ch0f tov1 ch1ie ch1max ch1f ch0max ms0b 16-bit counter internal bus bus clock t[1,2]ch0 interrupt logic port logic interrupt logic interrupt logic port logic t2clk ch01ie els0b els0a ms0a els0b els0a ms0a t[1,2]ch1 (for tim2 only) functional description mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 107 addr.register name bit 7654321bit 0 $0020 tim1 status and control register (t1sc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0021 tim1 counter register high (t1cnth) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $0022 tim1 counter register low (t1cntl) read:bit 7654321bit 0 write: reset:00000000 $0023 tim counter modulo register high (tmodh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 $0024 tim1 counter modulo register low (t1modl) read: bit 7654321bit 0 write: reset:11111111 $0025 tim1 channel 0 status and control register (t1sc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0026 tim1 channel 0 register high (t1ch0h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0027 tim1 channel 0 register low (t1ch0l) read: bit 7654321bit 0 write: reset: indeterminate after reset $0028 tim1 channel 1 status and control register (t1sc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $0029 tim1 channel 1 register high (t1ch1h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $002a tim1 channel 1 register low (t1ch1l) read: bit 7654321bit 0 write: reset: indeterminate after reset $0030 tim2 status and control register (t2sc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0031 tim2 counter register high (t2cnth) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $0032 tim2 counter register low (t2cntl) read:bit 7654321bit 0 write: reset:00000000 $0033 tim2 counter modulo register high (t2modh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 = unimplemented figure 8-2. tim i/o regist er summary (s heet 1 of 2) timer interface module (tim) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 108 freescale semiconductor 8.4.1 tim counter prescaler the tim1 clock source can be one of the seven prescaler outputs; tim2 clock source can be one of the seven prescaler outputs or the tim2 clock pin, t2cl k. the prescaler generates seven clock rates from the internal bus clock. the prescaler select bits, ps[2:0], in the tim status and control register select the tim clock source. 8.4.2 input capture with the input capture function, the tim can capture the time at which an external event occurs. when an active edge occurs on the pin of an input capture chann el, the tim latches the contents of the tim counter into the tim channel registers, tchxh:tchxl. the polarity of the active edge is programmable. input captures can generate tim cpu interrupt requests. 8.4.3 output compare with the output compare function, the tim can generat e a periodic pulse with a programmable polarity, duration, and frequency. when the counter reaches the value in the registers of an output compare channel, the tim can set, clear, or toggle the ch annel pin. output compares can generate tim cpu interrupt requests. $0034 tim2 counter modulo register low (t2modl) read: bit 7654321bit 0 write: reset:11111111 $0035 tim2 channel 0 status and control register (t2sc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0036 tim2 channel 0 register high (t2ch0h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0037 tim2 channel 0 register low (t2ch0l) read: bit 7654321bit 0 write: reset: indeterminate after reset $0038 tim2 channel 1 status and control register (t2sc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $0039 tim2 channel 1 register high (t2ch1h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $003a tim2 channel 1 register low (t2ch1l) read: bit 7654321bit 0 write: reset: indeterminate after reset addr.register name bit 7654321bit 0 = unimplemented figure 8-2. tim i/o regist er summary (s heet 2 of 2) functional description mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 109 8.4.3.1 unbuffered output compare any output compare channel can generate unbuffer ed output compare pulses as described in 8.4.3 output compare . the pulses are unbuffered because changing t he output compare value requires writing the new value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel regist ers to change an output compare value could cause incorrect operation for up to two counter overflow periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. also, using a tim overfl ow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. the tim may pass the new value before it is written. use the following methods to synchronize unbuffer ed changes in the output compare value on channel x: when changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse. the interrupt rout ine has until the end of the counter overflow period to write the new value. when changing to a larger output compare value, enable tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current counter overflow period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. 8.4.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the tch0 pin. the tim channel registers of t he linked pair alternately control the output. setting the ms0b bit in tim channel 0 status and control register (tsc 0) links channel 0 and channel 1. the output compare value in the tim channel 0 register s initially controls the output on the tch0 pin. writing to the tim channel 1 registers enables the tim channel 1 registers to synchronously control the output after the tim overflows. at each subsequent ov erflow, the tim channel registers (0 or 1) that control the output are the ones written to last. ts c0 controls and monitors the buffered output compare function, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, tch1, is available as a general-purpose i/o pin. note in buffered output compare operation, do not write new output compare values to the currently active channel registers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered output compares. 8.4.4 pulse widt h modulation (pwm) by using the toggle-on-overflow feature with an output compare channel, the tim can generate a pwm signal. the value in the tim counter modulo regi sters determines the period of the pwm signal. the channel pin toggles when the counter reaches the valu e in the tim counter modulo registers. the time between overflows is the period of the pwm signal. as figure 8-3 shows, the output compare value in the ti m channel registers determines the pulse width of the pwm signal. the time between overflow and out put compare is the pulse width. program the tim timer interface module (tim) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 110 freescale semiconductor to clear the channel pin on output compare if the stat e of the pwm pulse is logic 1. program the tim to set the pin if the state of the pwm pulse is logic 0. the value in the tim counter modulo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is variable in 256 increments. writing $00ff (255) to the tim counter modulo registers produces a pwm period of 256 times the internal bus clock period if the prescaler select value is $000. see 8.9.1 tim status and control register . figure 8-3. pwm period and pulse width the value in the tim channel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm signal is variable in 256 increments. writing $0080 (128) to the tim channel registers produces a duty cycle of 128/256 or 50%. 8.4.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 8.4.4 pulse width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel registers to change a pulse width value could cause incorrect operation for up to two pwm periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new va lue prevents any compare during that pwm period. also, using a tim overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. the tim may pass the new value before it is written. use the following methods to synchronize unbuffer ed changes in the pwm pulse width on channel x: when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pulse. the interrupt routine has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current pwm period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same pwm period. tchx period pulse width overflow overflow overflow output compare output compare output compare functional description mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 111 note in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare also can cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 8.4.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the tch0 pin. the tim channel registers of the linked pair alternately control the pulse width of the output. setting the ms0b bit in tim channel 0 status and control register (tsc 0) links channel 0 and channel 1. the tim channel 0 registers initially control the pulse width on the tch0 pin. writing to the tim channel 1 registers enables the tim channel 1 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tim channel registers (0 or 1) that control the pulse width are the ones written to last. tsc0 controls and monitors the buffered pwm function, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, tch1, is available as a general-purpose i/o pin. note in buffered pwm signal generation, do not write new pulse width values to the currently active channel regist ers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered pwm signals. 8.4.4.3 pwm initialization to ensure correct operation when generating unbuffered or buffered pwm signals, use the following initialization procedure: 1. in the tim status and control register (tsc): a. stop the tim counter by setting the tim stop bit, tstop. b. reset the tim counter and prescaler by setting the tim reset bit, trst. 2. in the tim counter modulo registers (tmodh:tmodl), write the value for the required pwm period. 3. in the tim channel x registers (tchxh:tchxl), write the value for the required pulse width. 4. in tim channel x status and control register (tscx): a. write 0:1 (for unbuffered output compare or pwm signals) or 1:0 (for buffered output compare or pwm signals) to the mode se lect bits, msxb:msxa. (see table 8-3 .) b. write 1 to the toggle-on-overflow bit, tovx. c. write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, elsxb:elsxa. the output action on compare must force the output to the complement of the pulse width level. (see table 8-3 .) note in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty timer interface module (tim) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 112 freescale semiconductor cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare can also cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the tim status control register (tsc), clear the tim stop bit, tstop. setting ms0b links channels 0 and 1 and configures them for buffered pwm operation. the tim channel 0 registers (tch0h:tch0l) initially control the bu ffered pwm output. tim status control register 0 (tscr0) controls and monitors the pwm signal from the linked channels. clearing the toggle-on-overflow bit, tovx, inhibits output toggles on tim overflows. subsequent output compares try to force the output to a state it is already in and have no effect. the result is a 0% duty cycle output. setting the channel x maximum duty cycle bit (chxmax) and setting the tovx bit generates a 100% duty cycle output. (see 8.9.4 tim channel status and control registers .) 8.5 interrupts the following tim sources can generate interrupt requests: tim overflow flag (tof) ? the tof bit is set when the tim counter reaches the modulo value programmed in the tim counter modulo registers. the tim overflow interrupt enable bit, toie, enables tim overflow cpu interrupt requests. tof and toie are in the tim status and control register. tim channel flags (ch1f:ch0f) ? the chxf bit is set when an input capture or output compare occurs on channel x. channel x tim cpu interr upt requests are controlled by the channel x interrupt enable bit, chxie. channel x tim cpu interrupt requests are enabled when chxie = 1. chxf and chxie are in the tim channel x status and control register. 8.6 low-power modes the wait and stop instructions put the mcu in low power- consumption standby modes. 8.6.1 wait mode the tim remains active after the execution of a wait instruction. in wait mode, the tim registers are not accessible by the cpu. any enabled cpu interrupt request from the tim can bring the mcu out of wait mode. if tim functions are not required during wait mode, r educe power consumption by stopping the tim before executing the wait instruction. 8.6.2 stop mode the tim is inactive after the execution of a stop instruction. the stop instruction does not affect register conditions or the state of the tim counter. tim operation resumes when the mcu exits stop mode after an external interrupt. tim during break interrupts mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 113 8.7 tim during break interrupts a break interrupt stops the tim counter. the system integration module (sim) controls whethe r status bits in other modules can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. (see 5.7.3 break flag control register (bfcr) .) to allow software to clear status bits during a break in terrupt, write a logic 1 to the bcfe bit. if a status bit is cleared during the break state, it rema ins cleared when the mcu exits the break state. to protect status bits during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), software can read and write i/o register s during the break state without affecting status bits. some status bits have a 2-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic 0. after the break, doing the second step clears the status bit. 8.8 i/o signals port d shares two of its pins with tim1 and port e shares two of its pins with tim2. the adc12/t2clk pin is an external clock input to tim2. the four tim channel i/o pins are t1ch0, t1ch1, t2ch0, and t2ch1. 8.8.1 tim clock pin (adc12/t2clk ) adc12/t2clk is an external clock input that can be the clock source for the tim2 counter instead of the prescaled internal bus clock. select the adc12/t2clk input by writing logic 1?s to the three prescaler select bits, ps[2:0]. (see 8.9.1 tim status and control register .) the minimum t2clk pulse width, t2clk lmin or t2clk hmin , is: the maximum t2clk frequency is: bus frequency timer interface module (tim) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 114 freescale semiconductor 8.9 i/o registers note references to either timer 1 or timer 2 may be made in the following text by omitting the timer number. for example, tsc may generically refer to both t1sc and t2sc. these i/o registers control and monitor operation of the tim: tim status and control register (tsc) tim counter registers (tcnth:tcntl) tim counter modulo registers (tmodh:tmodl) tim channel status and control registers (tsc0, tsc1) tim channel registers (tch0h:tch0l, tch1h:tch1l) 8.9.1 tim status and control register the tim status and control register (tsc): enables tim overflow interrupts flags tim overflows stops the tim counter resets the tim counter prescales the tim counter clock tof ? tim overflow flag bit this read/write flag is set when the tim counter reaches the modulo value programmed in the tim counter modulo registers. clear tof by reading the tim status and control register when tof is set and then writing a logic 0 to tof. if another tim overflow occurs before the clearing sequence is complete, then writing logic 0 to tof has no effect. therefore, a tof interrupt request cannot be lost due to inadvertent clearing of tof. reset clears th e tof bit. writing a logic 1 to tof has no effect. 1 = tim counter has reached modulo value 0 = tim counter has not reached modulo value toie ? tim overflow interrupt enable bit this read/write bit enables tim overflow interrupt s when the tof bit becom es set. reset clears the toie bit. 1 = tim overflow interrupts enabled 0 = tim overflow interrupts disabled address: t1sc, $0020 and t2sc, $0030 bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 = unimplemented figure 8-4. tim status and control register (tsc) i/o registers mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 115 tstop ? tim stop bit this read/write bit stops the tim counter. counting resumes when tstop is cleared. reset sets the tstop bit, stopping the tim counter until software clears the tstop bit. 1 = tim counter stopped 0 = tim counter active note do not set the tstop bit before entering wait mode if the tim is required to exit wait mode. trst ? tim reset bit setting this write-only bit resets the tim counter and the tim prescaler. setting trst has no effect on any other registers. counting resumes from $0000. trst is cleared automatically after the tim counter is reset and always reads as logic 0. reset clears the trst bit. 1 = prescaler and tim counter cleared 0 = no effect note setting the tstop and trst bits simultaneously stops the tim counter at a value of $0000. ps[2:0] ? prescaler select bits these read/write bits select one of the seven prescaler outputs as the input to the tim counter as table 8-2 shows. reset clears the ps[2:0] bits. 8.9.2 tim count er registers the two read-only tim counter registers contain the high and low bytes of the value in the tim counter. reading the high byte (tcnth) latches the contents of the low byte (tcntl) into a buffer. subsequent reads of tcnth do not affect the latched tcntl value until tcntl is read. reset clears the tim counter registers. setting the tim reset bit (trst) also clears the tim counter registers. note if you read tcnth during a break interrupt, be sure to unlatch tcntl by reading tcntl before exiting the break interrupt. otherwise, tcntl retains the value latched during the break. table 8-2. prescaler selection ps2 ps1 ps0 tim clock source 0 0 0 internal bus clock timer interface module (tim) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 116 freescale semiconductor 8.9.3 tim counter modulo registers the read/write tim modulo register s contain the modulo value for the tim counter. when the tim counter reaches the modulo value, the overflow flag (tof ) becomes set, and the tim counter resumes counting from $0000 at the next timer clock. writing to the hi gh byte (tmodh) inhibits the tof bit and overflow interrupts until the low byte (tmodl) is written. reset sets the tim counter modulo registers. note reset the tim counter before writing to the tim counter modulo registers. address: t1cnth, $0021 and t2cnth, $0031 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 = unimplemented figure 8-5. tim counter registers high (tcnth) address: t1cntl, $0022 and t2cntl, $0032 bit 7654321bit 0 read:bit 7654321bit 0 write: reset:00000000 = unimplemented figure 8-6. tim counter registers low (tcntl) address: t1modh, $0023 and t2modh, $0033 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 figure 8-7. tim counter modulo register high (tmodh) address: t1modl, $0024 and t2modl, $0034 bit 7654321bit 0 read: bit 7654321bit 0 write: reset:11111111 figure 8-8. tim counter modulo register low (tmodl) i/o registers mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 117 8.9.4 tim channel stat us and control registers each of the tim channel status and control registers: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or toggling output on output compare selects rising edge, falling edge, or any edge as the active input capture trigger selects output toggling on tim overflow selects 0% and 100% pwm duty cycle selects buffered or unbuffered output compare/pwm operation chxf ? channel x flag bit when channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output com pare channel, chxf is set when the value in the tim counter registers matches the value in the tim channel x registers. when tim cpu interrupt requests are enabled (chx ie = 1), clear chxf by reading tim channel x status and control register with chxf set and then wr iting a logic 0 to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing logic 0 to chxf has no effect. therefore, an interrupt request cannot be lost due to inadvertent clearing of chxf. reset clears the chxf bit. writing a logic 1 to chxf has no effect. 1 = input capture or output compare on channel x 0 = no input capture or output compare on channel x chxie ? channel x interrupt enable bit this read/write bit enables tim cpu interrupt service requests on channel x. reset clears the chxie bit. 1 = channel x cpu interrupt requests enabled 0 = channel x cpu interrupt requests disabled msxb ? mode select bit b this read/write bit selects buffered output compare/pwm operation. msxb exists only in the tim1 channel 0 and tim2 channel 0 status and control registers. address: t1sc0, $0025 and t2sc0, $0035 bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 figure 8-9. tim channel 0 status and control register (tsc0) address: t1sc1, $0028 and t2sc1, $0038 bit 7654321bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 figure 8-10. tim channel 1 status and control register (tsc1) timer interface module (tim) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 118 freescale semiconductor setting ms0b disables the channel 1 status and cont rol register and reverts tch1 to general-purpose i/o. reset clears the msxb bit. 1 = buffered output compare/pwm operation enabled 0 = buffered output compare/pwm operation disabled msxa ? mode select bit a when elsxb:elsxa note before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bits in the tim status and control register (tsc). elsxb and elsxa ? edge/level select bits when channel x is an input capture channel, these read/ write bits control the active edge-sensing logic on channel x. when channel x is an output compare channel, elsxb and elsxa control the channel x output behavior when an output compare occurs. when elsxb and elsxa are both clear, channel x is not connected to an i/o port, and pin tchx is available as a general-purpose i/o pin. table 8-3 shows how elsxb and elsxa work. reset clears the elsxb and elsxa bits. table 8-3. mode, edge, and level selection msxb:msxa elsxb:elsxa mode configuration x0 00 output preset pin under port control; initial output level high x1 00 pin under port control; initial output level low 00 01 input capture capture on rising edge only 00 10 capture on falling edge only 00 11 capture on rising or falling edge 01 01 output compare or pwm toggle output on compare 01 10 clear output on compare 01 11 set output on compare 1x 01 buffered output compare or buffered pwm toggle output on compare 1x 10 clear output on compare 1x 11 set output on compare i/o registers mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 119 note before enabling a tim channel register for input capture operation, make sure that the tchx pin is stable for at least two bus clocks. tovx ? toggle on overflow bit when channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the tim counter overflows. when c hannel x is an input capture channel, tovx has no effect. reset clears the tovx bit. 1 = channel x pin toggles on tim counter overflow 0 = channel x pin does not toggle on tim counter overflow note when tovx is set, a tim counter ov erflow takes precedence over a channel x output compare if both occur at the same time. chxmax ? channel x maximum duty cycle bit when the tovx bit is at logic 1, setting the chxmax bit forces the duty cycle of buffered and unbuffered pwm signals to 100%. as figure 8-11 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100% duty cycle level until the cycle after chxmax is cleared. figure 8-11. chxmax latency 8.9.5 tim channel registers these read/write registers contain the captured tim counter value of the input capture function or the output compare value of the output compare function. the state of the tim channel registers after reset is unknown. in input capture mode (msxb:msxa = 0:0), reading th e high byte of the tim channel x registers (tchxh) inhibits input captures until the low byte (tchxl) is read. in output compare mode (msxb:msxa timer interface module (tim) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 120 freescale semiconductor address: t1ch0h, $0026 and t2ch0h, $0036 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset figure 8-12. tim channel 0 register high (tch0h) address: t1ch0l, $0027 and t2ch0l $0037 bit 7654321bit 0 read: bit 7654321bit 0 write: reset: indeterminate after reset figure 8-13. tim channel 0 register low (tch0l) address: t1ch1h, $0029 and t2ch1h, $0039 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset figure 8-14. tim channel 1 register high (tch1h) address: t1ch1l, $002a and t2ch1l, $003a bit 7654321bit 0 read: bit 7654321bit 0 write: reset: indeterminate after reset figure 8-15. tim channel 1 register low (tch1l) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 121 chapter 9 serial communications interface (sci) 9.1 introduction this section describes the serial communications interface (sci) module, which allows high-speed asynchronous communications with peripheral devices and other mcus. 9.2 features features of the sci module include the following: full-duplex operation standard mark/space non-retu rn-to-zero (nrz) format 32 programmable baud rates programmable 8-bit or 9-bit character length separately enabled transmitter and receiver separate receiver and transmitter cpu interrupt requests programmable transmitter output polarity two receiver wakeup methods: ? idle line wakeup ? address mark wakeup interrupt-driven operation with eight interrupt flags: ? transmitter empty ? transmission complete ? receiver full ? idle receiver input ? receiver overrun ? noise error ? framing error ? parity error receiver framing error detection hardware parity checking 1/16 bit-time noise detection bus clock as baud rate clock source 9.3 pin name conventions the generic names of the sci i/o pins are: rxd (receive data) txd (transmit data) the sci i/o (input/output) lines are dedicated pins for the sci module. table 9-1 shows the full names and the generic names of the sci i/o pins. serial communications interface (sci) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 122 freescale semiconductor the generic pin names appear in the text of this section. figure 9-1. sci module block diagram table 9-1. pin name conventions generic pin names: rxd txd full pin names: ptd7/rxd ptd6/txd scte tc scrf idle or nf fe pe sctie tcie scrie ilie te re rwu sbk r8 t8 dmate orie feie peie bkf rpf sci data receive shift register sci data register transmit shift register neie m wake ilty flag control transmit control receive control data selection control wakeup pty pen register dma interrupt control transmitter interrupt control receiver interrupt control error interrupt control control dmare ensci loops ensci internal bus txinv loops 4 16 pre- scaler baud divider rxd txd bus clock functional description mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 123 9.4 functional description figure 9-1 shows the structure of the sci module. the sc i allows full-duplex, asynchronous, nrz serial communication among the mcu and remote devices, in cluding other mcus. the transmitter and receiver of the sci operate independently, although they use the same baud rate generator. during normal operation, the cpu monitors the status of the sci, writes the data to be transmitted, and processes received data. the baud rate clock source for the sci is the bus clock. 9.4.1 data format the sci uses the standard non-return-to-zero mark/space data format illustrated in figure 9-3 . figure 9-3. sci data formats addr.register name bit 7654321bit 0 $0013 sci control register 1 (scc1) read: loops ensci txinv m wake ilty pen pty write: reset:00000000 $0014 sci control register 2 (scc2) read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 $0015 sci control register 3 (scc3) read: r8 t8 dmare dmate orie neie feie peie write: reset:uu000000 $0016 sci status register 1 (scs1) read: scte tc scrf idle or nf fe pe write: reset:11000000 $0017 sci status register 2 (scs2) read: bkf rpf write: reset:00000000 $0018 sci data register (scdr) read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0019 sci baud rate register (scbr) read: 0 0 scp1 scp0 r scr2 scr1 scr0 write: reset:00000000 = unimplemented r = reserved u = unaffected figure 9-2. sci i/o register summary bit 5 start bit bit 0 bit 1 next stop bit start bit 8-bit data format bit m in scc1 clear start bit bit 0 next stop bit start bit 9-bit data format bit m in scc1 set bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 2 bit 3 bit 4 bit 6 bit 7 parity bit parity bit serial communications interface (sci) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 124 freescale semiconductor 9.4.2 transmitter figure 9-4 shows the structure of the sci transmitter. the baud rate clock source for the sci is the bus clock. figure 9-4. sci transmitter 9.4.2.1 character length the transmitter can accommodate either 8-bit or 9-bit data. the state of the m bit in sci control register 1 (scc1) determines character length. when transmitti ng 9-bit data, bit t8 in sci control register 3 (scc3) is the ninth bit (bit 8). 9.4.2.2 character transmission during an sci transmission, the transmit shift register sh ifts a character out to the txd pin. the sci data register (scdr) is the write-only buffer between the internal data bus and the transmit shift register. to initiate an sci transmission: dmate scte pen pty h876543210l 11-bit transmit stop start t8 dmate scte sctie tcie sbk tc parity generation msb sci data register load from scdr shift enable preamble all 1s break all 0s transmitter control logic shift register dmate tc sctie tcie scte transmitter cpu interrupt request transmitter dma service request m ensci loops te txinv internal bus 4 pre- scaler scp1 scp0 scr2 scr1 scr0 baud divider 16 sctie txd bus clock functional description mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 125 1. enable the sci by writing a logic 1 to the enable sci bit (ensci) in sci control register 1 (scc1). 2. enable the transmitter by writing a logic 1 to t he transmitter enable bit (te) in sci control register 2 (scc2). 3. clear the sci transmitter empty bit by first reading sci status register 1 (scs1) and then writing to the scdr. 4. repeat step 3 for each subsequent transmission. at the start of a transmission, transmitter control logi c automatically loads the tran smit shift register with a preamble of logic 1s. after the preamble shifts ou t, control logic transfers the scdr data into the transmit shift register. a logic 0 start bit automatically goes into the least significant bit position of the transmit shift register. a logic 1 stop bit goes into the most significant bit position. the sci transmitter empty bit, scte, in scs1 beco mes set when the scdr transfers a byte to the transmit shift register. the scte bi t indicates that the scdr can accept new data from the internal data bus. if the sci transmit interrupt enable bit, sctie, in scc2 is also set, the scte bit generates a transmitter cpu interrupt request. when the transmit shift register is not transmitting a character, the txd pin goes to the idle condition, logic 1. if at any time software clears the ensci bit in sci control register 1 (scc1), the transmitter and receiver relinquish control of the port pin. 9.4.2.3 break characters writing a logic 1 to the send break bit, sbk, in s cc2 loads the transmit shift register with a break character. a break character contains all logic 0s and has no start, stop, or parity bit. break character length depends on the m bit in scc1. as long as sbk is at logic 1, tran smitter logic cont inuously loads break characters into the transmit shift register. afte r software clears the sbk bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. the automatic logic 1 at the end of a break character guarantees the recogni tion of the start bit of the next character. the sci recognizes a break character when a start bit is followed by eight or ni ne logic 0 data bits and a logic 0 where the stop bit should be. receiving a break character has these effects on sci registers: sets the framing error bit (fe) in scs1 sets the sci receiver full bit (scrf) in scs1 clears the sci data register (scdr) clears the r8 bit in scc3 sets the break flag bit (bkf) in scs2 may set the overrun (or), noise flag (nf), parity error (pe), or reception in progress flag (rpf) bits 9.4.2.4 idle characters an idle character contains all logic 1s and has no st art, stop, or parity bit. idle character length depends on the m bit in scc1. the preamble is a synchronizing idle character that begins every transmission. if the te bit is cleared during a transmission, the txd pin become s idle after completion of the transmission in progress. clearing and then setting the te bit during a transmission queues an idle character to be sent after the character currently being transmitted. serial communications interface (sci) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 126 freescale semiconductor note when queueing an idle character, return the te bit to logic 1 before the stop bit of the current character shifts out to the txd pin. setting te after the stop bit appears on txd causes data previously written to the scdr to be lost. toggle the te bit for a queued idle character when the scte bit becomes set and just before writing the next byte to the scdr. 9.4.2.5 inversion of transmitted output the transmit inversion bit (txinv) in sci control regi ster 1 (scc1) reverses the polarity of transmitted data. all transmitted values, including idle, break, start, and stop bits, are inverted when txinv is at logic 1. (see 9.8.1 sci control register 1 .) 9.4.2.6 transmitter interrupts these conditions can generate cpu interrupt requests from the sci transmitter: sci transmitter empty (scte) ? the scte bit in scs1 indicates that the scdr has transferred a character to the transmit shift register. scte can generate a transmitter cpu interrupt request. setting the sci transmit interrupt enable bit, sctie, in scc2 enables the scte bit to generate transmitter cpu interrupt requests. transmission complete (tc) ? the tc bit in scs1 indicates that the transmit shift register and the scdr are empty and that no break or idle character has been generated. the transmission complete interrupt enable bit, tcie, in scc2 enables the tc bit to generate transmitter cpu interrupt requests. 9.4.3 receiver figure 9-5 shows the structure of the sci receiver. 9.4.3.1 character length the receiver can accommodate either 8-bit or 9-bit data . the state of the m bit in sci control register 1 (scc1) determines character length. when receiving 9-bi t data, bit r8 in sci control register 2 (scc2) is the ninth bit (bit 8). when receiving 8-bit data, bit r8 is a copy of the eighth bit (bit 7). 9.4.3.2 character reception during an sci reception, the receive shift regi ster shifts characters in from the rxd pin. the sci data register (scdr) is the read-only buffer between the internal data bus and the receive shift register. after a complete character shifts into the receive sh ift register, the data portion of the character transfers to the scdr. the sci receiver full bit, scrf, in sci status register 1 (scs1) becomes set, indicating that the received byte can be read. if th e sci receive interrupt enable bit, scrie, in scc2 is also set, the scrf bit generates a receiver cpu interrupt request. functional description mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 127 figure 9-5. sci receiver block diagram all 1s all 0s m wake ilty pen pty bkf rpf h876543210l 11-bit receive shift register stop start data recovery dmare scrf or orie nf neie fe feie pe peie dmare scrie scrf ilie idle wakeup logic parity checking msb error cpu interrupt request dma service request cpu interrupt request sci data register r8 dmare orie neie feie peie scrie ilie rwu scrf idle or nf fe pe internal bus pre- scaler baud divider 4 16 scp1 scp0 scr2 scr1 scr0 scrie dmare bus clock rxd serial communications interface (sci) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 128 freescale semiconductor 9.4.3.3 data sampling the receiver samples the rxd pin at the rt clock rate . the rt clock is an internal signal with a frequency 16 times the baud rate. to adjust for baud rate mismatch, the rt clock is resynchronized at the following times (see figure 9-6 ): after every start bit after the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at rt8, rt9, and rt10 returns a valid logic 1 and the majority of the next rt8, rt9, and rt10 samples returns a valid logic 0) to locate the start bit, data recovery logic does an a synchronous search for a logic 0 preceded by three logic 1s. when the falling edge of a possible start bit occurs, the rt clock begins to count to 16. figure 9-6. receiver data sampling to verify the start bit and to detect noise, data recovery logic takes samples at rt3, rt5, and rt7. table 9-2 summarizes the results of the start bit verification samples. start bit verification is not successful if any two of the three verification samples are logic 1s. if start bit verification is not successful, the rt clock is reset and a new search for a start bit begins. table 9-2. start bit verification rt3, rt5, and rt7 samples start bit verification noise flag 000 yes 0 001 yes 1 010 yes 1 011 no 0 100 yes 1 101 no 0 110 no 0 111 no 0 rt clock reset rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt8 rt7 rt6 rt11 rt10 rt9 rt15 rt14 rt13 rt12 rt16 rt1 rt2 rt3 rt4 start bit qualification start bit verification data sampling samples rt clock rt clock state start bit lsb rxd functional description mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 129 to determine the value of a data bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 9-3 summarizes the results of the data bit samples. note the rt8, rt9, and rt10 samples do not affect start bit verification. if any or all of the rt8, rt9, and rt10 start bit samples are logic 1s following a successful start bit verification, the noi se flag (nf) is set and the receiver assumes that the bit is a start bit. to verify a stop bit and to detect noise, recove ry logic takes samples at rt8, rt9, and rt10. table 9-4 summarizes the results of the stop bit samples. 9.4.3.4 framing errors if the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming character, it sets the framing error bit, fe, in scs1. a break ch aracter also sets the fe bit because a break character has no stop bit. the fe bit is set at t he same time that the scrf bit is set. table 9-3. data bit recovery rt8, rt9, and rt10 samples data bit determination noise flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 table 9-4. stop bit recovery rt8, rt9, and rt10 samples framing error flag noise flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0 serial communications interface (sci) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 130 freescale semiconductor 9.4.3.5 baud rate tolerance a transmitting device may be operating at a baud rate below or above the receiver baud rate. accumulated bit time misalignment can cause one of the three stop bi t data samples to fall outside the actual stop bit. then a noise error occurs. if more than one of the samples is outside the stop bit, a framing error occurs. in most applications, the baud rate tolerance is much more than the degree of misalignment that is likely to occur. as the receiver samples an incoming character, it resynchronizes the rt clock on any valid falling edge within the character. resynchronization within char acters corrects misalignments between transmitter bit times and receiver bit times. slow data tolerance figure 9-7 shows how much a slow received character can be misaligned without causing a noise error or a framing error. the slow stop bit begins at rt8 inst ead of rt1 but arrives in time for the stop bit data samples at rt8, rt9, and rt10. figure 9-7. slow data for an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times ? 154 ------------------------- - 100 ? 170 ------------------------- - 100 functional description mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 131 fast data tolerance figure 9-8 shows how much a fast received character c an be misaligned without causing a noise error or a framing error. the fast stop bit ends at rt10 in stead of rt16 but is still there for the stop bit data samples at rt8, rt9, and rt10. figure 9-8. fast data for an 8-bit character, data sampling of the stop bit takes the receiver 9bittimes 9.4.3.6 receiver wakeup so that the mcu can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. setting the receiver wakeup bit, rwu, in scc2 puts the receiver into a standby state during which receiver interrupts are disabled. depending on the state of the wake bi t in scc1, either of two conditio ns on the rxd pin can bring the receiver out of the standby state: idle or next character stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock 154 160 ? 154 ------------------------- - 100 = 170 176 ? 170 ------------------------- - 100 serial communications interface (sci) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 132 freescale semiconductor address mark ? an address mark is a logic 1 in the most significant bit position of a received character. when the wake bit is set, an address ma rk wakes the receiver from the standby state by clearing the rwu bit. the address mark also se ts the sci receiver full bit, scrf. software can then compare the character containing the addr ess mark to the user-defined address of the receiver. if they are the same, the receiver re mains awake and processes the characters that follow. if they are not the same, software can set the rwu bit and put the receiver back into the standby state. idle input line condition ? when the wake bit is clear, an idle character on the rxd pin wakes the receiver from the standby state by clearing the rwu bit. the idle character that wakes the receiver does not set the receiver idle bit, idle, or the sci receiver full bit, scrf. the idle line type bit, ilty, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit. note with the wake bit clear, setting the rwu bit after the rxd pin has been idle may cause the receiver to wake up immediately. 9.4.3.7 receiver interrupts the following sources can generate cpu interrupt requests from the sci receiver: sci receiver full (scrf) ? the scrf bit in scs1 indicates that the receive shift register has transferred a character to the scdr. scrf can generate a receiver cpu interrupt request. setting the sci receive interrupt enable bit, scrie, in scc2 enables the scrf bit to generate receiver cpu interrupts. idle input (idle) ? the idle bit in scs1 indicates that 10 or 11 consecutive logic 1s shifted in from the rxd pin. the idle line interrupt enable bi t, ilie, in scc2 enables the idle bit to generate cpu interrupt requests. 9.4.3.8 error interrupts the following receiver error flags in scs1 can generate cpu interrupt requests: receiver overrun (or) ? the or bit indicates t hat the receive shift register shifted in a new character before the previous c haracter was read from the scdr. the previous character remains in the scdr, and the new character is lost. th e overrun interrupt enable bit, orie, in scc3 enables or to generate sci error cpu interrupt requests. noise flag (nf) ? the nf bit is set when t he sci detects noise on incoming data or break characters, including start, data, and stop bits. the noise error interrupt enable bit, neie, in scc3 enables nf to generate sci error cpu interrupt requests. framing error (fe) ? the fe bit in scs1 is se t when a logic 0 occurs where the receiver expects a stop bit. the framing error interrupt enable bit, feie, in scc3 enables fe to generate sci error cpu interrupt requests. parity error (pe) ? the pe bit in scs1 is set when the sci detects a parity error in incoming data. the parity error interrupt enable bit, peie, in s cc3 enables pe to generate sci error cpu interrupt requests. low-power modes mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 133 9.5 low-power modes the wait and stop instructions put the mcu in low power- consumption standby modes. 9.5.1 wait mode the sci module remains active after the execution of a wait instruction. in wait mode, the sci module registers are not accessible by the cpu. any enabl ed cpu interrupt request from the sci module can bring the mcu out of wait mode. if sci module functions are not required during wait mode, reduce power consumption by disabling the module before executing the wait instruction. refer to 5.6 low-power modes for information on exiting wait mode. 9.5.2 stop mode the sci module is inactive after the execution of a stop instruction. the stop instruction does not affect sci register states. sci module operation resumes after an external interrupt. because the internal clock is inactive during st op mode, entering stop mode during an sci transmission or reception results in invalid data. refer to 5.6 low-power modes for information on exiting stop mode. 9.6 sci during bre ak module interrupts the system integration module (sim) controls whethe r status bits in other modules can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. to allow software to clear status bits during a break in terrupt, write a logic 1 to the bcfe bit. if a status bit is cleared during the break state, it rema ins cleared when the mcu exits the break state. to protect status bits during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), software can read and write i/o register s during the break state without affecting status bits. some status bits have a 2-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic 0. after the break, doing the second step clears the status bit. 9.7 i/o signals the two sci i/o pins are: ptd6/txd ? transmit data ptd7/rxd ? receive data 9.7.1 txd (transmit data) the ptd6/txd pin is the serial da ta output from the sci transmitter. 9.7.2 rxd (receive data) the ptd7/rxd pin is the serial data input to the sci receiver. serial communications interface (sci) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 134 freescale semiconductor 9.8 i/o registers these i/o registers control and monitor sci operation: sci control register 1 (scc1) sci control register 2 (scc2) sci control register 3 (scc3) sci status register 1 (scs1) sci status register 2 (scs2) sci data register (scdr) sci baud rate register (scbr) 9.8.1 sci control register 1 sci control register 1: enables loop mode operation enables the sci controls output polarity controls character length controls sci wakeup method controls idle character detection enables parity function controls parity type loops ? loop mode select bit this read/write bit enables loop mode operation. in loop mode the rxd pin is disconnected from the sci, and the transmitter output goes into the receiver input. both the transmitter and the receiver must be enabled to use loop mode. reset clears the loops bit. 1 = loop mode enabled 0 = normal operation enabled ensci ? enable sci bit this read/write bit enables the sci and the sci baud rate generator. clearing ensci sets the scte and tc bits in sci status register 1 and disables transmitter interrupts. reset clears the ensci bit. 1 = sci enabled 0 = sci disabled txinv ? transmit inversion bit this read/write bit reverses the polarity of transmitted data. reset clears the txinv bit. 1 = transmitter output inverted 0 = transmitter output not inverted note setting the txinv bit inverts all tran smitted values, including idle, break, start, and stop bits. address: $0013 bit 7654321bit 0 read: loops ensci txinv m wake ilty pen pty write: reset:00000000 figure 9-9. sci control register 1 (scc1) i/o registers mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 135 m ? mode (character length) bit this read/write bit determines whether sci c haracters are eight or nine bits long. (see table 9-5 .) the ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. reset clears the m bit. 1 = 9-bit sci characters 0 = 8-bit sci characters wake ? wakeup condition bit this read/write bit determines which condition wakes up the sci: a logic 1 (address mark) in the most significant bit position of a received character or an idle condition on the rxd pin. reset clears the wake bit. 1 = address mark wakeup 0 = idle line wakeup ilty ? idle line type bit this read/write bit determines when the sci starts coun ting logic 1s as idle character bits. the counting begins either after the start bit or after the stop bi t. if the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. beginning the count after the stop bit avoids false idle character recognition, but require s properly synchronized transmissions. reset clears the ilty bit. 1 = idle character bit count begins after stop bit 0 = idle character bit count begins after start bit pen ? parity enable bit this read/write bit enables the sci parity function. (see table 9-5 .) when enabled, the parity function inserts a parity bit in the most significant bit position. (see figure 9-3 .) reset clears the pen bit. 1 = parity function enabled 0 = parity function disabled pty ? parity bit this read/write bit determines whether the sci gen erates and checks for odd parity or even parity. (see table 9-5 .) reset clears the pty bit. 1 = odd parity 0 = even parity note changing the pty bit in the middle of a transmission or reception can generate a parity error. table 9-5. character format selection control bits character format m pen and pty start bits data bits parity stop bits character length 0 0x 1 8 none 1 10 bits 1 0x 1 9 none 1 11 bits 0 10 1 7 even 1 10 bits 0 11 1 7 odd 1 10 bits 1 10 1 8 even 1 11 bits 1 11 1 8 odd 1 11 bits serial communications interface (sci) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 136 freescale semiconductor 9.8.2 sci control register 2 sci control register 2: enables the following cpu interrupt requests: ? enables the scte bit to generate transmitter cpu interrupt requests ? enables the tc bit to generate transmitter cpu interrupt requests ? enables the scrf bit to generate receiver cpu interrupt requests ? enables the idle bit to generate receiver cpu interrupt requests enables the transmitter enables the receiver enables sci wakeup transmits sci break characters sctie ? sci transmit interrupt enable bit this read/write bit enables the scte bit to generate sci transmitter cpu interrupt requests. reset clears the sctie bit. 1 = scte enabled to generate cpu interrupt 0 = scte not enabled to generate cpu interrupt tcie ? transmission complete interrupt enable bit this read/write bit enables the tc bit to generate sci transmitter cpu interrupt requests. reset clears the tcie bit. 1 = tc enabled to generate cpu interrupt requests 0 = tc not enabled to generate cpu interrupt requests scrie ? sci receive interrupt enable bit this read/write bit enables the scrf bit to generate sci receiver cpu interrupt requests. reset clears the scrie bit. 1 = scrf enabled to generate cpu interrupt 0 = scrf not enabled to generate cpu interrupt ilie ? idle line interrupt enable bit this read/write bit enables the idle bit to generate sci receiver cpu interrupt requests. reset clears the ilie bit. 1 = idle enabled to generate cpu interrupt requests 0 = idle not enabled to generate cpu interrupt requests address: $0014 bit 7654321bit 0 read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 figure 9-10. sci control register 2 (scc2) i/o registers mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 137 te ? transmitter enable bit setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the transmit shift register to the txd pin. if software clears the te bit, the transmitter completes any transmission in progress before the txd returns to the idle condition (logic 1). clearing and then setting te during a transmission queues an id le character to be sent after the character currently being transmitted. reset clears the te bit. 1 = transmitter enabled 0 = transmitter disabled note writing to the te bit is not allowed when the enable sci bit (ensci) is clear. ensci is in sci control register 1. re ? receiver enable bit setting this read/write bit enables the receiver. clea ring the re bit disables the receiver but does not affect receiver interrupt flag bits. reset clears the re bit. 1 = receiver enabled 0 = receiver disabled note writing to the re bit is not allowe d when the enable sci bit (ensci) is clear. ensci is in sci control register 1. rwu ? receiver wakeup bit this read/write bit puts the receiver in a standby state during which receiver interrupts are disabled. the wake bit in scc1 determines whether an idle i nput or an address mark brings the receiver out of the standby state and clears the rwu bit. reset clears the rwu bit. 1 = standby state 0 = normal operation sbk ? send break bit setting and then clearing this read/writ e bit transmits a break character followed by a logic 1. the logic 1 after the break character guarantees recognition of a valid start bit. if sbk remains set, the transmitter continuously tr ansmits break characters with no logic 1s between them. reset clears the sbk bit. 1 = transmit break characters 0 = no break characters being transmitted note do not toggle the sbk bit immediately a fter setting the scte bit. toggling sbk before the preamble begins causes the sci to send a break character instead of a preamble. serial communications interface (sci) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 138 freescale semiconductor 9.8.3 sci control register 3 sci control register 3: stores the ninth sci data bit received and the ninth sci data bit to be transmitted enables these interrupts: ? receiver overrun interrupts ? noise error interrupts ? framing error interrupts parity error interrupts r8 ? received bit 8 when the sci is receiving 9-bit characters, r8 is the re ad-only ninth bit (bit 8) of the received character. r8 is received at the same time that the scdr receives the other 8 bits. when the sci is receiving 8-bit characters, r8 is a co py of the eighth bit (bit 7). reset has no effect on the r8 bit. t8 ? transmitted bit 8 when the sci is transmitting 9-bit characters, t8 is the read/write ninth bit (bit 8) of the transmitted character. t8 is loaded into the transmit shift regi ster at the same time that the scdr is loaded into the transmit shift register. rese t has no effect on the t8 bit. dmare ? dma receive enable bit caution the dma module is not included on this mcu. writing a logic 1 to dmare or dmate may adversely affect mcu performance. 1 = dma not enabled to service sci receiver dma serv ice requests generated by the scrf bit (sci receiver cpu interrupt requests enabled) 0 = dma not enabled to service sci receiver dma serv ice requests generated by the scrf bit (sci receiver cpu interrupt requests enabled) dmate ? dma transfer enable bit caution the dma module is not included on this mcu. writing a logic 1 to dmare or dmate may adversely affect mcu performance. 1 = scte dma service requests enabled; sc te cpu interrupt requests disabled 0 = scte dma service requests disabled ; scte cpu interrupt requests enabled orie ? receiver overrun interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the receiver overrun bit, or. 1 = sci error cpu interrupt requests from or bit enabled 0 = sci error cpu interrupt r equests from or bit disabled address: $0015 bit 7654321bit 0 read: r8 t8 dmare dmate orie neie feie peie write: reset:uu000000 = unimplemented u = unaffected figure 9-11. sci control register 3 (scc3) i/o registers mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 139 neie ? receiver noise error interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the noise error bit, ne. reset clears neie. 1 = sci error cpu interrupt requests from ne bit enabled 0 = sci error cpu interrupt requests from ne bit disabled feie ? receiver framing error interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the framing error bit, fe. reset clears feie. 1 = sci error cpu interrupt requests from fe bit enabled 0 = sci error cpu interrupt requests from fe bit disabled peie ? receiver parity error interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the parity error bit, pe. (see 9.8.4 sci status register 1 .) reset clears peie. 1 = sci error cpu interrupt requests from pe bit enabled 0 = sci error cpu interrupt requests from pe bit disabled 9.8.4 sci status register 1 sci status register 1 (scs1) contai ns flags to signal these conditions: transfer of scdr data to transmit shift register complete transmission complete transfer of receive shift register data to scdr complete receiver input idle receiver overrun noisy data framing error parity error scte ? sci transmitter empty bit this clearable, read-only bit is set when the scdr tr ansfers a character to the transmit shift register. scte can generate an sci transmitter cpu interrupt request. when the sctie bit in scc2 is set, scte generates an sci transmitter cpu interrupt reques t. in normal operation, clear the scte bit by reading scs1 with scte set and then wr iting to scdr. reset sets the scte bit. 1 = scdr data transferred to transmit shift register 0 = scdr data not transferred to transmit shift register address: $016 bit 7654321bit 0 read: scte tc scrf idle or nf fe pe write: reset:11000000 = unimplemented figure 9-12. sci status register 1 (scs1) serial communications interface (sci) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 140 freescale semiconductor tc ? transmission complete bit this read-only bit is set when the scte bit is se t, and no data, preamble, or break character is being transmitted. tc generates an sci transmitter cpu interrupt request if the tcie bit in scc2 is also set. tc is automatically cleared when data, preamble or break is queued and ready to be sent. there may be up to 1.5 transmitter clocks of latency be tween queueing data, preamble, and break and the transmission actually starti ng. reset sets the tc bit. 1 = no transmission in progress 0 = transmission in progress scrf ? sci receiver full bit this clearable, read-only bit is set when the data in the receive shift register transfers to the sci data register. scrf can generate an sci receiver cpu interrupt request. when the scrie bit in scc2 is set, scrf generates a cpu interrupt request. in normal operation, clear the scrf bit by reading scs1 with scrf set and then reading the scdr. reset clears scrf. 1 = received data available in scdr 0 = data not available in scdr idle ? receiver idle bit this clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input. idle generates an sci receiver cpu interrupt request if the ilie bit in scc2 is also set. clear the idle bit by reading scs1 with idle set and then reading the scdr. after the receiver is enabled, it must receive a valid character that sets the scrf bit befo re an idle condition can set the idle bit. also, after the idle bit has been cleared, a valid character mu st again set the scrf bit before an idle condition can set the idle bit. reset clears the idle bit. 1 = receiver input idle 0 = receiver input active (or id le since the idle bit was cleared) or ? receiver overrun bit this clearable, read-only bit is set when software fails to read the scdr before the receive shift register receives the next character. the or bit generates an sci error cpu interrupt request if the orie bit in scc3 is also set. the da ta in the shift register is lost, but the data already in the scdr is not affected. clear the or bit by reading scs1 with or set and then reading the scdr. reset clears the or bit. 1 = receive shift register full and scrf = 1 0 = no receiver overrun software latency may allow an ove rrun to occur between reads of sc s1 and scdr in the flag-clearing sequence. figure 9-13 shows the normal flag-clearing sequence and an example of an overrun caused by a delayed flag-clearin g sequence. the delayed read of scdr does not clear the or bit because or was not set when scs1 was read. byte 2 caused the overrun and is lost. the next flag-clearing sequence reads byte 3 in the scdr instead of byte 2. in applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun, the flag-clearing routine can check the or bit in a second read of scs1 after reading the data register. nf ? receiver noise flag bit this clearable, read-only bit is set when the sci detects noise on the rxd pin. nf generates an sci error cpu interrupt request if the neie bit in scc3 is also set. clear the nf bit by reading scs1 and then reading the scdr. reset clears the nf bit. 1 = noise detected 0 = no noise detected i/o registers mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 141 fe ? receiver framing error bit this clearable, read-only bit is set when a logic 0 is accepted as the stop bit. fe generates an sci error cpu interrupt request if the feie bit in scc3 also is set. clear the fe bit by reading scs1 with fe set and then reading the scdr. reset clears the fe bit. 1 = framing error detected 0 = no framing error detected figure 9-13. flag clearing sequence pe ? receiver parity error bit this clearable, read-only bit is set when the sci detects a parity error in incoming data. pe generates an sci error cpu interrupt request if the peie bit in scc3 is also set. clear the pe bit by reading scs1 with pe set and then reading the scdr. reset clears the pe bit. 1 = parity error detected 0 = no parity error detected byte 1 normal flag clearing sequence read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 0 read scdr byte 2 scrf = 0 read scs1 scrf = 1 or = 0 scrf = 1 scrf = 0 read scdr byte 3 scrf = 0 byte 1 read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 1 read scdr byte 3 delayed flag clearing sequence or = 1 scrf = 1 or = 1 scrf = 0 or = 1 scrf = 0 or = 0 serial communications interface (sci) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 142 freescale semiconductor 9.8.5 sci status register 2 sci status register 2 contains flags to signal the following conditions: break character detected incoming data bkf ? break flag bit this clearable, read-only bit is set when the sci detects a break character on the rxd pin. in scs1, the fe and scrf bits are also set. in 9-bit character transmissions, the r8 bit in scc3 is cleared. bkf does not generate a cpu interrupt request. clear bkf by reading scs2 with bkf set and then reading the scdr. once cleared, bkf can become set agai n only after logic 1s again appear on the rxd pin followed by another break character. reset clears the bkf bit. 1 = break character detected 0 = no break character detected rpf ? reception in progress flag bit this read-only bit is set when the receiver detects a logic 0 during the rt1 time period of the start bit search. rpf does not generate an interrupt request. rpf is reset after the receiver detects false start bits (usually from noise or a baud rate mismatch) or when the receiver detects an idle character. polling rpf before disabling the sci module or entering st op mode can show whether a reception is in progress. 1 = reception in progress 0 = no reception in progress 9.8.6 sci data register the sci data register (scdr) is the buffer between the internal data bus and the receive and transmit shift registers. reset has no effect on data in the sci data register. r7/t7?r0/t0 ? receive/transmit data bits reading the scdr accesses the read-only received da ta bits, r[7:0]. writing to the scdr writes the data to be transmitted, t[7:0]. reset has no effect on the scdr. note do not use read/modify/write instructions on the sci data register. address: $0017 bit 7654321bit 0 read: bkf rpf write: reset:00000000 = unimplemented figure 9-14. sci status register 2 (scs2) address: $0018 bit 7654321bit 0 read:r7r6r5r4r3r2r1r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset figure 9-15. sci data register (scdr) i/o registers mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 143 9.8.7 sci baud rate register the baud rate register (scbr) selects the baud rate for both the receiver and the transmitter. scp1 and scp0 ? sci baud rate prescaler bits these read/write bits select the baud rate prescaler divisor as shown in table 9-6 . reset clears scp1 and scp0. scr2?scr0 ? sci baud rate select bits these read/write bits select the sci baud rate divisor as shown in table 9-7 . reset clears scr2?scr0. use this formula to calculate the sci baud rate: where: sci clock source = bus clock pd = prescaler divisor bd = baud rate divisor table 9-8 shows the sci baud rates that can be generated with a 4.9152mhz bus clock. address: $0019 bit 7654321bit 0 read: 0 0 scp1 scp0 r scr2 scr1 scr0 write: reset:00000000 = unimplemented r = reserved figure 9-16. sci baud rate register (scbr) table 9-6. sci baud rate prescaling scp1 and scp0 prescaler divisor (pd) 00 1 01 3 10 4 11 13 table 9-7. sci baud rate selection scr2, scr1, and scr0 baud rate divisor (bd) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 baud rate sci clock source 64 pd bd serial communications interface (sci) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 144 freescale semiconductor table 9-8. sci baud rate selection examples scp1 and scp0 prescaler divisor (pd) scr2, scr1, and scr0 baud rate divisor (bd) baud rate (bus clock=4.9152mhz) 00 1 000 1 76,800 00 1 001 2 38,400 00 1 010 4 19,200 00 1 011 8 9,600 00 1 100 16 4,800 00 1 101 32 2,400 00 1 110 64 1,200 00 1 111 128 600 01 3 000 1 25,600 01 3 001 2 12,800 01 3 010 4 6,400 01 3 011 8 3,200 01 3 100 16 1,600 01 3 101 32 800 01 3 110 64 400 01 3 111 128 200 10 4 000 1 19,200 10 4 001 2 9,600 10 4 010 4 4,800 10 4 011 8 2,400 10 4 100 16 1,200 10 4 101 32 600 10 4 110 64 300 10 4 111 128 150 11 13 000 1 5,908 11 13 001 2 2,954 11 13 010 4 1,477 11 13 011 8 739 11 13 100 16 369 11 13 101 32 185 11 13 110 64 92 11 13 111 128 46 mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 145 chapter 10 analog-to-digital converter (adc) 10.1 introduction this section describes the 13-channel, 8-bit linear su ccessive approximation analog-to-digital converter (adc). 10.2 features features of the adc module include: 13 channels with multiplexed input linear successive approxi mation with monotonicity 8-bit resolution single or continuous conversion conversion complete flag or conversion complete interrupt 10.3 functional description thirteen adc channels are available for sampling ex ternal sources at pins ptb0?ptb7, ptd0?ptd3, and adc12/t2clk. an analog multiplexer allows the single adc converter to select one of the 13 adc channels as adc voltage input (adcvin). adcvin is converted by the successive approximation register-based counters. the adc resolution is 8 bits . when the conversion is completed, adc puts the result in the adc data register and sets a flag or generates an interrupt. figure 10-2 shows a block diagram of the adc. addr.register name bit 7654321bit 0 $003c adc status and control register (adscr) read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 $003d adc data register (adr) read:ad7ad6ad5ad4ad3ad2ad1ad0 write: reset: indeterminate after reset $003e adc input clock register (adiclk) read: adiv2 adiv1 adiv0 00000 write: reset:00000000 figure 10-1. adc i/o register summary analog-to-digital converter (adc) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 146 freescale semiconductor figure 10-2. adc block diagram 10.3.1 adc port i/o pins ptb0?ptb7 and ptd0?ptd3 are general-purpose i/o pi ns that are shared with the adc channels. the channel select bits (adc status and control regist er, $003c), define which a dc channel/port pin will be used as the input signal. the adc overrides the port i/o logic by forcing that pin as input to the adc. the remaining adc channels/port pins are controlle d by the port i/o logic and can be used as general-purpose i/o. writes to the port register or ddr will not have any affect on the port pin that is selected by the adc. read of a port pin which is in use by the adc will return a logic 0 if the corresponding ddr bit is at logic 0. if the ddr bit is at logi c 1, the value in the port data latch is read. internal data bus interrupt logic channel select adc clock generator conversion complete adc voltage in adcvin adc clock bus clock adch[4:0] adc data register adiv[2:0] aien coco disable disable adc channel x read ddrb/ddrd write ddrb/ddrd reset write ptb/ptd read ptb/ptd ddrbx/ddrdx ptbx/ptdx (1 of 13 channels) adcx adc0?adc11 adc12 interrupts mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 147 10.3.2 voltage conversion when the input voltage to the adc equals v dd , the adc converts the signal to $ff (full scale). if the input voltage equals v ss , the adc converts it to $ 00. input voltages between v dd and v ss are a straight-line linear conversion. all other input voltages will result in $ff if greater than v dd and $00 if less than v ss . note input voltage should not exc eed the analog supply voltages. 10.3.3 conversion time fourteen adc internal clocks are required to perf orm one conversion. the adc starts a conversion on the first rising edge of the adc internal clock immedi ately following a write to the adscr. if the adc internal clock is selected to run at 1mhz, then one conversion will take 14 analog-to-digital converter (adc) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 148 freescale semiconductor 10.5.2 stop mode the adc module is inactive after the execution of a stop instruction. any pending conversion is aborted. adc conversions resume when the mcu exits stop mode. allow one conversion cycle to stabilize the analog circuitry before attempting a new adc conversion after exiting stop mode. 10.6 i/o signals the adc module has 12 channels that are shared with i/o port b and port d, and one channel on adc12/t2clk pin. 10.6.1 adc volt age in (adcvin) adcvin is the input voltage signal from one of the 13 adc channels to the adc module. 10.7 i/o registers these i/o registers control and monitor adc operation: adc status and control register (adscr) adc data register (adr) adc clock register (adiclk) 10.7.1 adc status and control register the following paragraphs describe the functi on of the adc status and control register. coco ? conversions complete bit when the aien bit is a logic 0, the coco is a r ead-only bit which is set each time a conversion is completed. this bit is cleared whenever the adc status and control register is written or whenever the adc data register is read. reset clears this bit. 1 = conversion completed (aien = 0) 0 = conversion not completed (aien = 0) when the aien bit is a logic 1 (cpu interrupt enabl ed), the coco is a read -only bit, and will always be logic 0 when read. aien ? adc interrupt enable bit when this bit is set, an interrupt is generated at th e end of an adc conversion. the interrupt signal is cleared when the data register is read or the status/control register is written. reset clears the aien bit. 1 = adc interrupt enabled 0 = adc interrupt disabled address: $003c bit 7654321bit 0 read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 = unimplemented figure 10-3. adc status and control register (adscr) i/o registers mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 149 adco ? adc continuous conversion bit when set, the adc will convert samples continuously and update the adr register at the end of each conversion. only one conver sion is allowed when this bit is cleared. reset clears the adco bit. 1 = continuous adc conversion 0 = one adc conversion adch[4:0] ? adc channel select bits adch[4:0] form a 5-bit field which is used to select one of the adc channels. the five channel select bits are detailed in the following table. care s hould be taken when using a port pin as both an analog and a digital input simultaneously to prevent switching noise from corrupting the analog signal. (see table 10-1 .) the adc subsystem is turned off when the channel select bits are all set to one. this feature allows for reduced power consumption for the mcu when the adc is not used. reset sets all of these bits to a logic 1. note recovery from the disabled state requi res one conversion cycle to stabilize. table 10-1. mux channel select adch4 adch3 adch2 ad ch1 adch0 adc channel input select 00000adc0 ptb0 00001adc1 ptb1 00010adc2 ptb2 00011adc3 ptb3 00100adc4 ptb4 00101adc5 ptb5 00110adc6 ptb6 00111adc7 ptb7 01000adc8 ptd3 01001adc9 ptd2 01010adc10 ptd1 01011adc11 ptd0 01100adc12 adc12/t2clk 01101 unused (1) 1. if any unused channels are selected, th e resulting adc conversion will be unknown. ::::: ? 11010 11011 ? reserved 11 1 0 0 ? reserved 11 1 0 1 v dd (2) 2. the voltage levels supplied from internal reference nodes as specified in the table are used to verify the operation of the adc converter both in pr oduction test and for user applications. 11 1 1 0 v ss (2) 11 1 1 1 adc power off analog-to-digital converter (adc) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 150 freescale semiconductor 10.7.2 adc data register one 8-bit result register is provided. this regi ster is updated each time an adc conversion completes. 10.7.3 adc input clock register this register selects the clock frequency for the adc. adiv[2:0] ? adc clock prescaler bits adiv[2:0] form a 3-bit field which selects the divide ratio used by the adc to generate the internal adc clock. table 10-2 shows the available clock configurati ons. the adc clock should be set to approximately 1mhz. address: $003d bit 7654321bit 0 read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: indeterminate after reset = unimplemented figure 10-4. adc data register (adr) address: $003e bit 7654321bit 0 read: adiv2 adiv1 adiv0 00000 write: reset:00000000 = unimplemented figure 10-5. adc input clock register (adiclk) table 10-2. adc clock divide ratio adiv2 adiv1 adiv0 adc clock rate 0 0 0 bus clock 1 0 0 1 bus clock 2 0 1 0 bus clock 4 0 1 1 bus clock 8 1 x x bus clock 16 x = don?t care mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 151 chapter 11 input/output (i/o) ports 11.1 introduction twenty six (26) bidirectional input- output (i/o) pins form four parallel ports. all i/o pins are programmable as inputs or outputs. note connect any unused i/o pins to an appropriate logic level, either v dd or v ss . although the i/o ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. addr.register name bit 7654321bit 0 $0000 port a data register (pta) read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0003 port d data register (ptd) read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset $0004 data direction register a (ddra) read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0007 data direction register d (ddrd) read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 $0008 port e data register (pte) read: pte1 pte0 write: reset: unaffected by reset $000a port d control register (pdcr) read: 0000 slowd7 slowd6 ptdpu7 ptdpu6 write: reset: 00000000 $000c data direction register e (ddre) read: ddre1 ddre0 write: reset:00000000 figure 11-1. i/o port register summary input/output (i/o) ports mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 152 freescale semiconductor $000d port a input pull-up enable register (ptapue) read: pta6en ptapue6 ptapue5 ptapue4 ptapue3 ptapue2 ptapue1 ptapue0 write: reset:00000000 $000e pta7 input pull-up enable register (pta7pue) read: ptapue7 write: reset:00000000 table 11-1. port control register bits summary port bit ddr module control pin module register control bit a 0 ddra0 kbi kbier ($001b) kbie0 pta0/kbi0 1 ddra1 kbie1 pta1/kbi1 2 ddra2 kbie2 pta2/kbi2 3 ddra3 kbie3 pta3/kbi3 4 ddra4 kbie4 pta4/kbi4 5 ddra5 kbie5 pta5/kbi5 6 ddra6 osc kbi ptapue ($000d) kbier ($001b) pta6en kbie6 rcclk/pta6/kbi6 (1) 1. rcclk/pta6/kbi6 pin is only available when oscsel=0 (rc option); ptapue register has priority control over the port pin. rcclk/pta6/kbi6 is the osc2 pin when oscsel=1 (xtal option). 7 ddra7 kbi kbier ($001b) kbie7 pta7/kbi7 b 0 ddrb0 adc adscr ($003c) adch[4:0] ptb0/adc0 1 ddrb1 ptb1/adc1 2 ddrb2 ptb2/adc2 3 ddrb3 ptb3/adc3 4 ddrb4 ptb4/adc4 5 ddrb5 ptb5/adc5 6 ddrb6 ptb6/adc6 7 ddrb7 ptb7/adc7 d 0 ddrd0 adc adscr ($003c) adch[4:0] ptd0/adc11 1 ddrd1 ptd1/adc10 2 ddrd2 ptd2/adc9 3 ddrd3 ptd3/adc8 4 ddrd4 tim1 t1sc0 ($0025) els0b:els0a ptd4/t1ch0 5 ddrd5 t1sc1 ($0028) els1b:els1a ptd5/t1ch1 6 ddrd6 sci scc1 ($0013) ensci ptd6/txd 7 ddrd7 ptd7/rxd e 0 ddre0 tim2 t2sc0 ($0035) els0b:els0a pte0/t2ch0 1 ddre1 t2sc1 ($0038) el s1b:els1a pte1/t2ch1 addr.register name bit 7654321bit 0 figure 11-1. i/o port register summary port a mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 153 11.2 port a port a is an 8-bit special function port that shares all of its pins with the keyboard interrupt (kbi) module (see chapter 13 keyboard interrupt module (kbi) ). each port a pin also has software configurable pull-up device if the corresponding port pin is configured as input port. pta0?pta5 and pta7 has direct led drive capability. note pta0?pta5 pins are available on 28-pin and 32-pin packages only. pta7 pin is available on 32-pin packages only. 11.2.1 port a data register (pta) the port a data register (pta) contains a data latch for each of the eight port a pins. pta[7:0] ? port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction regi ster a. reset has no effect on port a data. kbi7?kbi0 ? port a keyboard interrupts the keyboard interrupt enable bits, kbie[7:0], in the keyboard interrupt control register (kbier) enable the port a pins as external interrupt pins, (see chapter 13 keyboard interrupt module (kbi) ). 11.2.2 data directio n register a (ddra) data direction register a determines whether each port a pin is an input or an output. writing a logic 1 to a ddra bit enables the output buffer for the corresponding port a pin; a logic 0 disables the output buffer. note for those devices packaged in a 28-pin package, pta7 is not connected. ddra7 should be set to a 1 to configure pta7 as an output. for those devices packaged in a 20-pin package, pta0?pta5 and pta7 are not connected. ddra0?ddra5 and ddra7 should be set to a 1 to configure pta0?pta5 and pta7 as outputs. address: $0000 bit 76 5 4 3 2 1bit 0 read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset additional functions: led (sink) led (sink) led (sink) led (sink) led (sink) led (sink) led (sink) pull-up pull-up pull-up pull-up pull-up pull-up pull-up pull-up alternative functions: keyboard interrupt keyboard interrupt keyboard interrupt keyboard interrupt keyboard interrupt keyboard interrupt keyboard interrupt keyboard interrupt figure 11-2. port a data register (pta) input/output (i/o) ports mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 154 freescale semiconductor ddra[7:0] ? data direction register a bits these read/write bits contro l port a data direction. reset clears ddra[7:0], configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note avoid glitches on port a pins by writin g to the port a data register before changing data direction regist er a bits from 0 to 1. figure 11-4 shows the port a i/o logic. figure 11-4. port a i/o circuit when ddrax is a logic 1, reading address $0000 reads the pt ax data latch. when ddrax is a logic 0, reading address $0000 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 11-2 summarizes the operation of the port a pins. address: $0004 bit 7654321bit 0 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 figure 11-3. data direction register a (ddra) table 11-2. port a pin functions ptapue bit ddra bit pta bit i/o pin mode accesses to ddra accesses to pta read/write read write 10 x (1) 1. x = don?t care. input, v dd (2) 2. pin pulled to v dd by internal pull-up. ddra[7:0] pin pta[7:0] (3) 3. writing affects data register, but does not affect input. 00x input, hi-z (4) 4. hi-z = high impedance. ddra[7:0] pin pta[7:0] (3) x 1 x output ddra[7:0] pta[7:0] pta[7:0] read ddra ($0004) write ddra ($0004) reset write pta ($0000) read pta ($0000) ptax ddrax ptax internal data bus ptapuex to kbi port a mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 155 11.2.3 port a input pu ll-up enable registers the port a input pull-up enable registers contain a so ftware configurable pull-up device for each of the eight port a pins. each bit is individually conf igurable and requires the corresponding data direction register, ddrax be configured as input. each pul l-up device is automatically disabled when its corresponding ddrax bit is configured as output. pta6en ? enable pta6 on osc2 this read/write bit configures the osc2 pin function when rc oscillator option is selected. this bit has no effect for xtal oscillator option. 1 = osc2 pin configured for pta6 i/o, and has all the interrupt and pull-up functions 0 = osc2 pin outputs the rc oscillator clock (rcclk) ptapue[7:0] ? port a input pull-up enable bits these read/write bits are software programma ble to enable pull-up devices on port a pins. 1 = corresponding port a pin configured to have internal pull-up if its ddra bit is set to 0 0 = pull-up device is disconnected on the corresponding port a pin regardless of the state of its ddra bit address: $000d bit 7654321bit 0 read: pta6en ptapue6 ptapue5 ptapue4 ptapue3 ptapue2 ptapue1 ptapue0 write: reset:00000000 figure 11-5. port a input pull-up enable register (ptapue) address: $000e bit 7654321bit 0 read: ptapue7 write: reset:00000000 figure 11-6. pta7 input pull-up enable register (pta7pue) input/output (i/o) ports mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 156 freescale semiconductor 11.3 port b port b is an 8-bit special function port that shares all of its port pins with the analog-to-digital converter (adc) module, see chapter 10 11.3.1 port b data register (ptb) the port b data register contains a data latch for each of the eight port b pins. ptb[7:0] ? port b data bits these read/write bits are software programmable. data direction of each port b pin is under the control of the corresponding bit in data direction regi ster b. reset has no effect on port b data. adc7?adc0 ? adc channels 7 to 0 adc7?adc0 are pins used for the input channels to the analog-to-digital converter module. the channel select bits, adch[4:0], in the adc status and control register define which port pin will be used as an adc input and overrides any control from the port i/o logic. see chapter 10 analog-to-digital converter (adc) . 11.3.2 data directio n register b (ddrb) data direction register b determines whether each port b pin is an input or an output. writing a logic 1 to a ddrb bit enables the output buffer for the corresponding port b pin; a logic 0 disables the output buffer. ddrb[7:0] ? data direction register b bits these read/write bits contro l port b data direction. reset clears ddrb[7:0], configuring all port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note avoid glitches on port b pins by writin g to the port b data register before changing data direction regist er b bits from 0 to 1. figure 11-9 shows the port b i/o logic. address: $0001 bit 76 5 4 3 2 1bit 0 read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset alternative functions: adc7 adc6 adc5 adc4 adc3 adc2 adc2 adc0 figure 11-7. port b data register (ptb) address: $0005 bit 7654321bit 0 read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 figure 11-8. data direction register b (ddrb) port d mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 157 figure 11-9. port b i/o circuit when ddrbx is a logic 1, reading address $0001 reads the pt bx data latch. when ddrbx is a logic 0, reading address $0001 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 11-3 summarizes the operation of the port b pins. 11.4 port d port d is an 8-bit special function port that shares two of its pins with the se rial communications interface module (see chapter 9 ), two of its pins with the timer 1 interface module, (see chapter 8 ), and four of its pins with the analog-to-digital converter module (see chapter 10 ). ptd6 and ptd7 each has high current sink (25ma) and programmable pull-up. ptd2, ptd3 , ptd6 and ptd7 each has led sink capability. note ptd0?ptd1 are available on 28- pin and 32-pin packages only. table 11-3. port b pin functions ddrb bit ptb bit i/o pin mode accesses to ddrb accesses to ptb read/write read write 0x (1) 1. x = don?t care. input, hi-z (2) 2. hi-z = high impedance. ddrb[7:0] pin ptb[7:0] (3) 3. writing affects data register, but does not affect the input. 1 x output ddrb[7:0] ptb[7:0] ptb[7:0] read ddrb ($0005) write ddrb ($0005) reset write ptb ($0001) read ptb ($0001) ptbx ddrbx ptbx internal data bus to analog-to-digital converter input/output (i/o) ports mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 158 freescale semiconductor 11.4.1 port d data register (ptd) the port d data register contains a data latch for each of the eight port d pins. ptd[7:0] ? port d data bits these read/write bits are software programmable. data direction of each port d pin is under the control of the corresponding bit in data direction register d. reset has no effect on port d data. adc11?adc8 ? adc channels 11 to 8 adc[11:8] are pins used for the input channels to the analog-to-digital converter module. the channel select bits, adch[4:0], in the adc status and control register define which port pin will be used as an adc input and overrides any control from the port i/o logic. see chapter 10 analog-to-digital converter (adc) . t1ch1, t1ch0 ? timer 1 channel i/os the t1ch1 and t1ch0 pins are the tim1 input capture/output compare pins. the edge/level select bits, elsxb:elsxa, determine whether the ptd4/t1 ch0 and ptd5/t1ch1 pins are timer channel i/o pins or general-purpose i/o pins. see chapter 8 timer interface module (tim) . txd, rxd ? sci data i/o pins the txd and rxd pins are the transmit data output and receive data input for the sci module. the enable sci bit, ensci, in the sci control register 1 enables the ptd6/txd and ptd7/rxd pins as sci txd and rxd pins and overrides any cont rol from the port i/o logic. see chapter 9 serial communications interface (sci) . 11.4.2 data directio n register d (ddrd) data direction register d determines whether each por t d pin is an input or an output. writing a logic 1 to a ddrd bit enables the output buffer for the corresponding port d pin; a logic 0 disables the output buffer. note for those devices packaged in a 20-pin package , ptd0?ptd1 and are not connected. ddrd0?ddrd1 should be set to a 1 to configure ptd0?ptd1 as outputs. address: $0003 bit 76 5 4 3 2 1bit 0 read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset additional functions led (sink) led (sink) led (sink) led (sink) 25ma sink (slow edge) 25ma sink (slow edge) pull-up pull-up alternative functions: rxd txd t1ch1 t1ch0 adc8 adc9 adc10 adc11 figure 11-10. port d data register (ptd) port d mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 159 ddrd[7:0] ? data direction register d bits these read/write bits control port d data direction. reset clears ddrd[7:0], configuring all port d pins as inputs. 1 = corresponding port d pin configured as output 0 = corresponding port d pin configured as input note avoid glitches on port d pins by writin g to the port d data register before changing data direction regist er d bits from 0 to 1. figure 11-12 shows the port d i/o logic. figure 11-12. port d i/o circuit when ddrdx is a logic 1, reading address $0003 reads the ptdx data latch. when ddrdx is a logic 0, reading address $0003 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 11-4 summarizes the operation of the port d pins. address: $0007 bit 7654321bit 0 read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 figure 11-11. data direction register d (ddrd) table 11-4. port d pin functions ddrd bit ptd bit i/o pin mode accesses to ddrd accesses to ptd read/write read write 0x (1) 1. x = don?t care. input, hi-z (2) 2. hi-z = high impedance. ddrd[7:0] pin ptd[7:0] (3) 3. writing affects data register, but does not affect the input. 1 x output ddrd[7:0] ptd[7:0] ptd[7:0] read ddrd ($0007) write ddrd ($0007) reset write ptd ($0003) read ptd ($0003) ptdx ddrdx ptdx internal data bus to adc, tim1, sci ptdpu[6:7] input/output (i/o) ports mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 160 freescale semiconductor 11.4.3 port d cont rol register (pdcr) the port d control register enables/disables the pul l-up resistor and slow-edge high current capability of pins ptd6 and ptd7. slowdx ? slow edge enable the slowd6 and slowd7 bits enable the slow-edge, open-drain, high current output (25ma sink) of port pins ptd6 and ptd7 respectively . ddrdx bit is not affected by slowdx. 1 = slow edge enabled; pin is open-drain output 0 = slow edge disabled; pi n is push-pull (standard i/o) ptdpux ? port d pull-up enable bits the ptdpu6 and ptdpu7 bits enable the pull-up dev ice on ptd6 and ptd7 respectively, regardless the status of ddrdx bit. 1 = enable pull-up device 0 = disable pull-up device 11.5 port e port e is a 2-bit special function port that shares its pins with the timer 2 interface module (see chapter 8 ). note pte0?pte1 are available on 32-pin packages only. 11.5.1 port e data register (pte) the port e data register contains a data latch for each of the two port e pins. pte[1:0] ? port e data bits these read/write bits are software programmable. data direction of each port e pin is under the control of the corresponding bit in data direction regi ster e. reset has no effect on port d data. address: $000a bit 7654321bit 0 read: 0 0 0 0 slowd7 slowd6 ptdpu7 ptdpu6 write: reset:00000000 figure 11-13. port d control register (pdcr) address: $0008 bit 76 5 4 3 2 1bit 0 read: pte1 pte0 write: reset: unaffected by reset alternative functions: t2ch1 t2ch0 figure 11-14. port e data register (pte) port e mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 161 t2ch1, t2ch0 ? timer 2 channel i/os the t2ch1 and t2ch0 pins are the tim2 input capture/output compare pins. the edge/level select bits, elsxb:elsxa, determine whether the pte0/t2 ch0 and pte1/t2ch1 pins are timer channel i/o pins or general-purpose i/o pins. see chapter 8 timer interface module (tim) . 11.5.2 data directio n register e (ddre) data direction register e determines whether each port e pin is an input or an output. writing a logic 1 to a ddre bit enables the output buffer for the corresponding port e pin; a logic 0 disables the output buffer. note for those devices packaged in a 20-pin package a nd 28-pin package, pte0?pte1 are not connected. ddre0?ddre1 should be set to a 1 to configure pte0?p te1 as outputs. ddre[1:0] ? data direction register e bits these read/write bits contro l port e data direction. reset clears ddre[1:0], configuring all port e pins as inputs. 1 = corresponding port e pin configured as output 0 = corresponding port e pin configured as input note avoid glitches on port e pins by writin g to the port e data register before changing data direction register e bits from 0 to 1. figure 11-16 shows the port e i/o logic. figure 11-16. port e i/o circuit address: $000c bit 7654321bit 0 read: ddre1 ddre0 write: reset:00000000 figure 11-15. data direction register e (ddre) read ddre ($000c) write ddre ($000c) reset write pte ($0008) read pte ($0008) ptex ddrex ptex internal data bus to ti m2 input/output (i/o) ports mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 162 freescale semiconductor when ddrex is a logic 1, reading address $0008 reads the pt ex data latch. when ddrex is a logic 0, reading address $0008 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 11-5 summarizes the operation of the port e pins. table 11-5. port e pin functions ddre bit pte bit i/o pin mode accesses to ddre accesses to pte read/write read write 0x (1) 1. x = don?t care. input, hi-z (2) 2. hi-z = high impedance. ddre[1:0] pin pte[1:0] (3) 3. writing affects data register, but does not affect the input. 1 x output ddre[1:0] pte[1:0] pte[1:0] mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 163 chapter 12 external interrupt (irq) 12.1 introduction the external interrupt (irq) module provides a maskable interrupt input. 12.2 features features of the irq module include the following: a dedicated external interrupt pin (irq ) irq interrupt control bits hysteresis buffer programmable edge-only or edge and level interrupt sensitivity automatic interrupt acknowledge selectable internal pullup resistor 12.3 functional description a logic zero applied to the external interr upt pin can latch a cpu interrupt request. figure 12-1 shows the structure of the irq module. interrupt signals on the irq pin are latched into the irq latch. an interrupt latch remains set until one of the following actions occurs: vector fetch ? a vector fetch automatically gener ates an interrupt acknowledge signal that clears the irq latch. software clear ? software can clear the interrupt latch by writing to the acknowledge bit in the interrupt status and control register (intscr). writing a logic one to the ack bit clears the irq latch. reset ? a reset automatically clears the interrupt latch. the external interrupt pin is falling-edge-triggered and is software-configurable to be either falling-edge or falling-edge and low-level-triggered. the mode bit in the intscr controls the triggering sensitivity of the irq pin. when the interrupt pin is edge-triggered only, the cpu interrupt request remains set until a vector fetch, software clear, or reset occurs. when the interrupt pin is both falling-edge and low-level-triggered, the cpu interrupt request remains set until both of the following occur: vector fetch or software clear return of the interrupt pin to logic one external interrupt (irq) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 164 freescale semiconductor the vector fetch or software clear may occur before or after the interrupt pin returns to logic one. as long as the pin is low, the interrupt request remains pendi ng. a reset will clear the latch and the mode control bit, thereby clearing the interrupt even if the pin stays low. when set, the imask bit in the intscr mask all exte rnal interrupt requests. a latched interrupt request is not presented to the interrupt priori ty logic unless the imask bit is clear. note the interrupt mask (i) in the condi tion code register (ccr) masks all interrupt requests, including external interrupt requests. (see 5.5 exception control .) figure 12-1. irq module block diagram 12.3.1 irq pin a logic zero on the irq pin can latch an interrupt request into the irq latch. a vector fetch, software clear, or reset clears the irq latch. if the mode bit is set, the irq pin is both falling-edge-sensitive a nd low-level-sensitive. with mode set, both of the following actions must occur to clear irq: addr.register name bit 7654321bit 0 $001d irq status and control register (intscr) read:0000irqf0 imask mode write: ack reset:00000000 = unimplemented figure 12-2. irq i/o register summary imask dq ck clr irq high interrupt to mode select logic request v dd mode voltage detect irqf to cpu for bil/bih instructions vector fetch decoder internal address bus reset ack irq synchronizer internal pullup device v dd irqpud irq module during break interrupts mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 165 vector fetch or software clear ? a vector fetch generates an interrupt acknowledge signal to clear the latch. software may generate the interrupt ac knowledge signal by writing a logic one to the ack bit in the interrupt status and control register (intscr). the ack bit is useful in applications that poll the irq pin and require software to clear the irq latch. writing to the ack bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. setting ack does not affect subsequent transitions on the irq pin. a falling edge that occurs after writing to the ack bit latches another interrupt r equest. if the irq mask bit, imask, is clear, the cpu loads the program counter with the vector address at locations $fffa and $fffb. return of the irq pin to logic one ? as long as the irq pin is at logic zero, irq remains active. the vector fetch or software clear and the return of the irq pin to logic one may occur in any order. the interrupt request remains pending as long as the irq pin is at logic zero. a reset will clear the latch and the mode control bit, thereby clearing the interrupt even if the pin stays low. if the mode bit is clear, the irq pin is falling-edge-sensitive only. with mode clear, a vector fetch or software clear immediately clears the irq latch. the irqf bit in the intscr register can be used to check for pending interrupts. the irqf bit is not affected by the imask bit, which makes it usef ul in applications where polling is preferred. use the bih or bil instruction to read the logic level on the irq pin. note when using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. note an internal pull-up resistor to v dd is connected to the irq pin; this can be disabled by setting the irqpud bit in the config2 register ($001e). 12.4 irq module du ring break interrupts the system integration module (sim ) controls whether the irq latch can be cleared during the break state. the bcfe bit in the break flag control regist er (bfcr) enables software to clear the latches during the break state. (see chapter 5 system integration module (sim) .) to allow software to clear the irq latch during a break interrupt, write a logic one to the bcfe bit. if a latch is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the latches during the break state, write a logic zero to the bcfe bit. with bcfe at logic zero (its default state), writing to the ack bit in the irq status and control register during the break state has no effect on the irq latch. external interrupt (irq) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 166 freescale semiconductor 12.5 irq status and co ntrol register (intscr) the irq status and control register (intscr) contro ls and monitors operation of the irq module. the intscr has the following functions: shows the state of the irq flag clears the irq latch masks irq and interrupt request controls triggering sensitivity of the irq interrupt pin irqf ? irq flag bit this read-only status bit is high when the irq interrupt is pending. 1 = irq interrupt pending 0 = irq interrupt not pending ack ? irq interrupt request acknowledge bit writing a logic one to this write-only bit clears the irq latch. ack always r eads as logic zero. reset clears ack. imask ? irq interrupt mask bit writing a logic one to this read/write bit dis ables irq interrupt requests. reset clears imask. 1 = irq interrupt requests disabled 0 = irq interrupt requests enabled mode ? irq edge/level select bit this read/write bit controls the triggering sensitivity of the irq pin. reset clears mode. 1 = irq interrupt requests on falling edges and low levels 0 = irq interrupt requests on falling edges only irqpud ? irq pin pull-up disable bit irqpud disconnects the internal pull-up on the irq pin. 1 = internal pull-up is disconnected 0 = internal pull-up is connected between irq pin and v dd address: $001d bit 7654321bit 0 read:0000irqf imask mode write: ack reset:00000000 = unimplemented figure 12-3. irq status and control register (intscr) address: $001e bit 7654321bit 0 read: irqpudrrlvit1lvit0rrr write: reset:000 not affected not affected 000 por:00000000 r=reserved figure 12-4. configuration register 2 (config2) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 167 chapter 13 keyboard interrupt module (kbi) 13.1 introduction the keyboard interrupt module (kbi) provides eight independently maskable external interrupts which are accessible via pta0?pta7. when a port pin is enabled for keyboard interrupt function, an internal pull-up device is also enabled on the pin. 13.2 features features of the keyboard interrupt module include the following: eight keyboard interrupt pins with pull-up devices separate keyboard interrupt enable bits and one keyboard interrupt mask programmable edge-only or edge- and level- interrupt sensitivity exit from low-power modes 13.3 i/o pins the eight keyboard interrupt pins are shared with st andard port i/o pins. the full name of the kbi pins are listed in table 13-1 . the generic pin name appear in the text that follows. addr.register name bit 7654321bit 0 $001a keyboard status and control register (kbscr) read:0000keyf0 imaskk modek write: ackk reset:00000000 $001b keyboard interrupt enable register (kbier) read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 = unimplemented figure 13-1. kbi i/o register summary table 13-1. pin name conventions kbi generic pin name full mcu pin name pin selected for kbi function by kbiex bit in kbier kbi0?kbi5 pta0/kbi0?pta5/kbi5 kbie0?kbie5 kbi6 osc2/rcclk/pta6/kbi6 (1) 1. pta6/kbi6 is only available when oscsel=0 at $ffd0 (rc option), and pta6en=1 at $000d. kbie6 kbi7 pta7/kbi7 kbie7 keyboard interrupt module (kbi) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 168 freescale semiconductor 13.4 functional description figure 13-2. keyboard interrupt block diagram writing to the kbie7?kbie0 bits in the keyboard interrupt enable register independently enables or disables each port a pin as a keyboard interrupt pin. enabling a keyboard interrupt pin in port a also enables its internal pull-up device regardless of ptapuex bits in the port a input pull-up enable register (see 11.2.3 port a input pull-up enable registers ). a logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. a keyboard interrupt is latched when one or more keyb oard pins goes low after all were high. the modek bit in the keyboard status and control register cont rols the triggering mode of the keyboard interrupt. if the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low. to prevent losing an interrupt request on one pin because another pin is still low, softwar e can disable the latter pin while it is low. if the keyboard interrupt is falling edge- and low level-sensitive, an interrupt request is present as long as any keyboard pin is low. if the modek bit is set, the keyboard interrupt pins are both falling edge- and low level-sensitive, and both of the following actions must occur to clear a keyboard interrupt request: vector fetch or software clear ? a vector fetch generates an interrupt acknowledge signal to clear the interrupt request. software may generate the in terrupt acknowledge signal by writing a logic 1 to the ackk bit in the keyboard status and control register kbscr. the ackk bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. writing to the ackk bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. setting ackk does not affect subsequent transitions on the keyboard interrupt pins. a falling edge that oc curs after writing to the ackk bit latches another interrupt request. if the keyboard interrupt mask bit, imaskk, is clear, the cpu loads the program counter with the vector address at locations $ffe0 and $ffe1. return of all enabled keyboard interrupt pins to logic 1 ? as long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. the vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. kbie0 kbie7 . . . dq ck clr v dd modek imaskk keyboard interrupt ff vector fetch decoder ackk internal bus reset kbi7 kbi0 synchronizer keyf keyboard interrupt request to pullup enable to pullup enable note: to prevent false interrupts, user should use software to debounce keyboard interrupt inputs. keyboard interrupt registers mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 169 if the modek bit is clear, the keyboard interrupt pin is falling-edge-sensitive only. with modek clear, a vector fetch or software clear immediately clears the keyboard interrupt request. reset clears the keyboard interrupt request and the mo dek bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. the keyboard flag bit (keyf) in the keyboard status and control register can be used to see if a pending interrupt exists. the keyf bit is not affected by t he keyboard interrupt mask bit (imaskk) which makes it useful in applications where polling is preferred. to determine the logic level on a keyboard interrupt pin, disable the pull-up devic e, use the data direction register to configure the pin as an input and then read the data register. note setting a keyboard interrupt enable bi t (kbiex) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. however, the data direction register bit must be a logic 0 for software to read the pin. 13.4.1 keyboard initialization when a keyboard interrupt pin is enabled, it takes time for the internal pull-up to reach a logic 1. therefore a false interrupt can occur as soon as the pin is enabled. to prevent a false interrupt on keyboard initialization: 1. mask keyboard interrupts by setting the imaskk bit in the keyboard status and control register. 2. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 3. write to the ackk bit in the keyboard status and control register to clear any false interrupts. 4. clear the imaskk bit. an interrupt signal on an edge-triggered pin can be acknowledged immediately a fter enabling the pin. an interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. another way to avoid a false interrupt: 1. configure the keyboard pins as outputs by setting the appropr iate ddra bits in the data direction register a. 2. write logic 1?s to the appropriate port a data register bits. 3. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 13.5 keyboard in terrupt registers two registers control the operation of the keyboard interrupt module: keyboard status and control register keyboard interrupt enable register 13.5.1 keyboard stat us and control register flags keyboard interrupt requests acknowledges keyboard interrupt requests masks keyboard interrupt requests controls keyboard interrupt triggering sensitivity keyboard interrupt module (kbi) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 170 freescale semiconductor keyf ? keyboard flag bit this read-only bit is set when a keyboard interrupt is pending on port a. reset clears the keyf bit. 1 = keyboard interrupt pending 0 = no keyboard interrupt pending ackk ? keyboard acknowledge bit writing a logic 1 to this write-only bit clears the keyboard interrupt request on port a. ackk always reads as logic 0. reset clears ackk. imaskk? keyboard interrupt mask bit writing a logic 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests on port a. reset clears the imaskk bit. 1 = keyboard interrupt requests masked 0 = keyboard interrupt requests not masked modek ? keyboard triggering sensitivity bit this read/write bit controls the triggering sensitivity of the keyboard interrupt pins on port a. reset clears modek. 1 = keyboard interrupt requests on falling edges and low levels 0 = keyboard interrupt requests on falling edges only 13.5.2 keyboard inte rrupt enable register the port-a keyboard interrupt enable register enables or disables each port-a pin to operate as a keyboard interrupt pin kbie7?kbie0 ? port-a keyboard interrupt enable bits each of these read/write bits enables the corre sponding keyboard interrupt pin on port-a to latch interrupt requests. reset clears the keyboard interrupt enable register. 1 = kbix pin enabled as keyboard interrupt pin 0 = kbix pin not enabled as keyboard interrupt pin address: $001a bit 7654321bit 0 read:0000keyf0 imaskk modek write: ackk reset:00000000 = unimplemented figure 13-3. keyboard status and control register (kbscr) address: $001b bit 7654321bit 0 read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 figure 13-4. keyboard interrupt enable register (kbier) low-power modes mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 171 13.6 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 13.6.1 wait mode the keyboard modules remain active in wait mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of wait mode. 13.6.2 stop mode the keyboard module remain s active in stop mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of stop mode. 13.7 keyboard module during break interrupts the system integration module (sim) controls whet her the keyboard interrupt latch can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. to allow software to clear the keyboard interrupt latch during a break interrupt, write a logic 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the latch during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), writing to the keyboard acknowledge bit (ackk) in the keyboard status and control register during the break state has no effect. keyboard interrupt module (kbi) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 172 freescale semiconductor mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 173 chapter 14 computer operating properly (cop) 14.1 introduction the computer operating properly (cop) module cont ains a free-running counter that generates a reset if allowed to overflow. the cop modul e helps software recover from runaway code. prevent a cop reset by clearing the cop counter periodically. the cop m odule can be disabled through the copd bit in the config1 register. 14.2 functional description figure 14-1 shows the structure of the cop module. figure 14-1. cop block diagram copctl write iclk reset vector fetch sim reset circuit reset status register internal reset sources (1) sim clear stages 5?12 12-bit sim counter clear all stages copd (from config1) reset copctl write clear cop module copen (from sim) cop counter note: see sim section for more details. cop clock cop timeout cop rate sel (coprs from config1) 6-bit cop counter computer operating properly (cop) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 174 freescale semiconductor the cop counter is a free-running 6-bit counter prec eded by the 12-bit system integration module (sim) counter. if not cleared by software, the cop counter overflows and generates an asynchronous reset after 2 18 ?2 4 or 2 13 ?2 4 iclk cycles; depending on the state of the cop rate select bit, coprs, in configuration register 1. writing any value to locati on $ffff before an overflow occurs prevents a cop reset by clearing the cop counter and stages 12 through 5 of the sim counter. note service the cop immediately after rese t and before entering or after exiting stop mode to guarantee the maximum time before the first cop counter overflow. a cop reset pulls the rst pin low for 32 note place cop clearing instructions in the main program and not in an interrupt subroutine. such an interrupt s ubroutine could keep the cop from generating a reset even while the main program is not working properly. 14.3 i/o signals the following paragraphs describe the signals shown in figure 14-1 . 14.3.1 iclk iclk is the internal oscillator output signal, typica lly 50-khz. the iclk frequency varies depending on the supply voltage. see chapter 17 electrical specifications for iclk parameters. 14.3.2 copctl write writing any value to the cop control register (copctl) (see 14.4 cop control register ) clears the cop counter and clears bits 12 through 5 of the sim counter. reading the cop control register returns the low byte of the reset vector. 14.3.3 power-on reset the power-on reset (por) circuit in the sim clears the sim counter 4096 cop control register mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 175 14.3.7 coprs (cop rate select) the coprs signal reflects the state of the cop rate select bit (coprs) in the configuration register 1. coprs ? cop rate select bit coprs selects the cop timeout period. reset clears coprs. 1 = cop timeout period is (2 13 ? 2 4 ) iclk cycles 0 = cop timeout period is (2 18 ? 2 4 ) iclk cycles copd ? cop disable bit copd disables the cop module. 1 = cop module disabled 0 = cop module enabled 14.4 cop control register the cop control register is located at address $ffff and overlaps the reset vector. writing any value to $ffff clears the cop counter and starts a new timeout period. reading location $ffff returns the low byte of the reset vector. 14.5 interrupts the cop does not generate cpu interrupt requests. 14.6 monitor mode the cop is disabled in monitor mode when v tst is present on the irq pin or on the rst pin. 14.7 low-power modes the wait and stop instructions put the mcu in low-power consumption standby modes. address: $001f bit 7654321bit 0 read: coprs r r lvid r ssrec stop copd write: reset:00000000 r=reserved figure 14-2. configuration register 1 (config1) address: $ffff bit 7654321bit 0 read: low byte of reset vector write: clear cop counter reset: unaffected by reset figure 14-3. cop control register (copctl) computer operating properly (cop) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 176 freescale semiconductor 14.7.1 wait mode the cop continues to operate during wait mode. to prevent a cop reset during wait mode, periodically clear the cop counter in a cpu interrupt routine. 14.7.2 stop mode stop mode turns off the iclk input to the cop and clears the cop prescaler. service the cop immediately before entering or after exiting stop mode to ensure a full cop timeout period after entering or exiting stop mode. to prevent inadvertently turning off the cop with a stop instruction, a configuration option is available that disables the stop instruction. when the stop bit in the configuration register has the stop instruction is disabled, execution of a stop instruction results in an illegal opcode reset. 14.8 cop module during break mode the cop is disabled during a break interrupt when v tst is present on the rst pin. mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 177 chapter 15 low voltage inhibit (lvi) 15.1 introduction this section describes the low-voltage inhibit m odule (lvi), which monitors the voltage on the v dd pin and generates a reset when the v dd voltage falls to the lvi trip (lvi trip ) voltage. 15.2 features features of the lvi module include the following: selectable lvi trip voltage selectable lvi circuit disable 15.3 functional description figure 15-1 shows the structure of the lvi module. the lvi is enabled after a reset. the lvi module contains a bandgap reference circuit and comparator. setti ng lvi disable bit (lvid) disables the lvi to monitor v dd voltage. the lvi trip voltage selection bits (lvit1, lvit0) determine at which v dd level the lvi module should take actions. the lvi module generates one output signal: lvi reset ? an reset signal will be generated to reset the cpu when v dd drops to below the set trip point. figure 15-1. lvi module block diagram low v dd lv i t 1 lv i d detector v dd lvi reset lv i t 0 v dd > lvi trip = 0 v dd < lvi trip = 1 low voltage inhibit (lvi) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 178 freescale semiconductor 15.4 lvi control regi ster (config2/config1) the lvi module is controlled by three bits in the configuration registers, config1 and config2. lvid ? low voltage inhibit disable bit lvid disables the lvi module. reset clears lvid. 1 = low voltage inhibit disabled 0 = low voltage inhibit enabled lvit1, lvit0 ? lvi trip voltage selection bits these two bits determine at which level of v dd the lvi module will come into action. lvit1 and lvit0 are cleared by a power-on reset only. 15.5 low-power modes the stop and wait instructions put the mcu in low-power-consumption standby modes. 15.5.1 wait mode the lvi module, when enabled, will continue to operate in wait mode. 15.5.2 stop mode the lvi module, when enabled, will continue to operate in stop mode. address: $001e bit 7654321bit 0 read: irqpud r r lvit1 lvit0 r r stop_ iclkdis write: reset:000 cleared by por only 000 figure 15-2. configuration register 2 (config2) address: $001f bit 7654321bit 0 read: coprs r r lvid r ssrec stop copd write: reset:00000000 figure 15-3. configuration register 1 (config1) table 15-1. trip voltage selection lvit1 lvit0 trip voltage (1) 1. see chapter 17 electrical specifications for full parameters. comments 00 v lv r 3 (2.49v) for v dd =3v operation 01 v lv r 3 (2.49v) for v dd =3v operation 10 v lv r 5 (4.25v) for v dd =5v operation 11 reserved mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 179 chapter 16 break module (break) 16.1 introduction this section describes the break module. the brea k module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. 16.2 features features of the break module include the following: accessible i/o registers during the break interrupt cpu-generated break interrupts software-generated break interrupts cop disabling during break interrupts 16.3 functional description when the internal address bus matches the value writt en in the break address registers, the break module issues a breakpoint signal (bkpt ) to the sim. the sim then causes the cpu to load the instruction register with a software interrupt instruction (swi) after completion of the current cpu instruction. the program counter vectors to $fffc and $fffd ($fefc and $fefd in monitor mode). the following events can cause a break interrupt to occur: a cpu-generated address (the address in the program counter) matches the contents of the break address registers. software writes a logic one to the brka bit in the break status and control register. when a cpu generated address matches the contents of t he break address registers, the break interrupt begins after the cpu completes its current instruction. a return from interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation. figure 16-1 shows the structure of the break module. figure 16-1. break module block diagram iab[15:8] 8-bit comparator 8-bit comparator control break address register low break address register high iab[15:0] bkpt (to sim) iab[7:0] break module (break) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 180 freescale semiconductor 16.3.1 flag protectio n during break interrupts the system integration module (sim) controls whether or not module status bits can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. (see 5.7.3 break flag control register (bfcr) and see the break interrupts subsection for each module.) 16.3.2 cpu during break interrupts the cpu starts a break interrupt by: loading the instruction register with the swi instruction loading the program counter with $fffc:$fffd ($fefc:$fefd in monitor mode) the break interrupt begins after completion of the cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu in struction, the break inte rrupt begins immediately. 16.3.3 tim during break interrupts a break interrupt stops the timer counter. 16.3.4 cop during break interrupts the cop is disabled during a break interrupt when v tst is present on the rst pin. addr.register name bit 7654321bit 0 $fe00 break status register (bsr) read: rrrrrr sbsw r write: see note reset: 0 $fe03 break flag control register (bfcr) read: bcferrrrrrr write: reset: 0 $fe0c break address high register (brkh) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 $fe0d break address low register (brkl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:00000000 $fe0e break status and control register (brkscr) read: brke brka 000000 write: reset:00000000 note: writing a logic 0 clears sbsw. = unimplemented r = reserved figure 16-2. break i/ o register summary break module registers mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 181 16.4 break module registers these registers control and monitor operation of the break module: break status and control register (brkscr) break address register high (brkh) break address register low (brkl) break status register (bsr) break flag control register (bfcr) 16.4.1 break status and control register (brkscr) the break status and control register cont ains break module enable and status bits. brke ? break enable bit this read/write bit enables breaks on break addres s register matches. clear brke by writing a logic zero to bit 7. reset clears the brke bit. 1 = breaks enabled on 16-bit address match 0 = breaks disabled brka ? break active bit this read/write status and control bit is set when a break address match occurs. writing a logic one to brka generates a break interrupt. clear brka by writ ing a logic zero to it before exiting the break routine. reset clears the brka bit. 1 = break address match 0 = no break address match 16.4.2 break addr ess registers the break address registers contain the high and lo w bytes of the desired breakpoint address. reset clears the break address registers. address: $fe0e bit 7654321bit 0 read: brke brka 000000 write: reset:00000000 = unimplemented figure 16-3. break status and control register (brkscr) address: $fe0c bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 figure 16-4. break address register high (brkh) break module (break) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 182 freescale semiconductor 16.4.3 break status register the break status register contains a flag to indicate that a break caused an exit from stop or wait mode. sbsw ? sim break stop/wait this status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. clear sbsw by writing a l ogic zero to it. reset clears sbsw. 1 = stop mode or wait mode was exited by break interrupt 0 = stop mode or wait mode was not exited by break interrupt sbsw can be read within the break state swi routine. the user can modify t he return address on the stack by subtracting one from it. the following code is an example of this. address: $fe0d bit 7654321bit 0 read: bit 7654321bit 0 write: reset:00000000 figure 16-5. break address register low (brkl) address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note (1) reset: 0 r = reserved 1. writing a logic zero clears sbsw. figure 16-6. break status register (bsr) ; ; ; this code works if the h register has been pushed onto the stack in the break service routine software. this code should be executed at the end of the break service routine software. hibyte equ 5 lobyte equ 6 ; if not sbsw, do rti brclr sbsw,bsr, return ; ; see if wait mode or stop mode was exited by break. tst lobyte,sp ; if returnlo is not zero, bne dolo ; then just decrement low byte. dec hibyte,sp ; else deal with high byte, too. dolo dec lobyte,sp ; point to wait/stop opcode. return pulh rti ; restore h register. low-power modes mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 183 16.4.4 break flag cont rol register (bfcr) the break control register contains a bit that enables software to clear status bits while the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bi ts by accessing status r egisters while the mcu is in a break state. to clear status bits duri ng the break state, the bcfe bit must be set. 1 = status bits cl earable during break 0 = status bits not clearable during break 16.5 low-power modes the wait and stop instructions put the mcu in low-power-consumption standby modes. 16.5.1 wait mode if enabled, the break module is active in wait mode. in the break routine, the user can subtract one from the return address on the stack if sbsw is set (see 5.6 low-power modes ). clear the sbsw bit by writing logic zero to it. 16.5.2 stop mode a break interrupt causes exit from stop mode and sets the sbsw bit in the break status register. see 5.7 sim registers . address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r= reserved figure 16-7. break flag control register (bfcr) break module (break) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 184 freescale semiconductor mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 185 chapter 17 electrical specifications 17.1 introduction this section contains electrical and timing specifications. 17.2 absolute maximum ratings maximum ratings are the extreme limits to which t he mcu can be exposed without permanently damaging it. note this device is not guaranteed to operate properly at the maximum ratings. refer to sections 17.5 and 17.8 for guaranteed operating conditions. note this device contains circuitry to pr otect the inputs against damage due to high static voltages or electric fields ; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either v ss or v dd .) table 17-1. absolute maximum ratings characteristic (1) 1. voltages referenced to v ss . symbol value unit supply voltage v dd ?0.3 to +6.0 v input voltage v in v ss ?0.3 to v dd +0.3 v mode entry voltage, irq pin v tst v ss ?0.3 to +8.5 v maximum current per pin excluding v dd and v ss i electrical specifications mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 186 freescale semiconductor 17.3 functional operating range 17.4 thermal characteristics table 17-2. operating range characteristic symbol value unit operating temperature range t a ? 40 to +125 ? 40 to +85 c) w constant (2) 2. k constant unique to the devic e. k can be determined for a known t a and measured p d . with this value of k, p d and t j can be determined for any value of t a . k p d x (t a + 273 c ) + p d 2 ja w/ ja ) 5v dc electrical characteristics mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 187 17.5 5v dc electrical characteristics table 17-4. dc electrical characteristics (5v) characteristic (1) 1. v dd = 4.5 to 5.5 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. symbol min typ (2) 2. typical values reflect average measur ements at midpoint of voltage range, 25 ? ? electrical specifications mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 188 freescale semiconductor 17.6 5v control timing figure 17-1. rst and irq timing 17.7 5v oscillator characteristics table 17-5. control timing (5v) characteristic (1) 1. v dd = 4.5 to 5.5 vdc, v ss = 0 vdc, t a = t l to t h ; timing shown with respect to 20% v dd and 70% v ss , unless otherwise noted. symbol min max unit internal operating frequency f op ?8mhz rst input pulse width low (2) 2. minimum pulse width reset is guaranteed to be recognized. it is possible for a smaller pulse width to cause a reset. t rl 750 ? ns tim2 external clock input f t2clk ?4mhz irq interrupt pulse width low (edge-triggered) (3) 3. values are based on characterizati on results, not tested in production. t ilih 100 ? ns irq interrupt pulse period (3) t ilil note (4) 4. the minimum period is the number of cycles it take s to execute the interrupt service routine plus 1 t cyc . ?t cyc table 17-6. oscillator specifications (5v) characteristic symbol min typ max unit internal oscillator clock frequency f iclk 50k (1) 1. typical value reflect average measuremen ts at midpoint of voltage range, 25 ? ? rst irq t rl t ilih t ilil 3v dc electrical characteristics mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 189 figure 17-2. rc vs. frequency (5v @25 r ext c ext osc1 v dd mcu 0 01020304050 14 12 10 8 6 4 2 resistor, r ext (k ? electrical specifications mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 190 freescale semiconductor 17.9 3v control timing figure 17-3. rst and irq timing capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf por rearm voltage (6) v por 0?100mv por rise time ramp rate (7) r por 0.035 ? ? v/ms monitor mode entry voltage v tst 1.5 ? ? rst irq t rl t ilih t ilil 3v oscillator characteristics mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 191 17.10 3v oscillator characteristics figure 17-4. rc vs. frequency (3v @25 ? ? r ext c ext osc1 v dd mcu 0 0 1020304050 14 12 10 8 6 4 2 resistor, r ext (k ? electrical specifications mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 192 freescale semiconductor figure 17-5. internal oscillator frequency 17.11 typical supply currents figure 17-6. typical operating i dd (xtal osc), with all modules turned on (25 timer interface module characteristics mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 193 17.12 timer interface module characteristics 17.13 adc characteristics table 17-10. timer interface module characteristics (5v and 3v) characteristic symbol min max unit input capture pulse width t tih, t til 1/f op ? input clock pulse width (t2clk pulse width) t lmin, t hmin (1/f op ) + 5ns ? table 17-11. adc characteristics (5v and 3v) characteristic symbol min max unit comments supply voltage v ddad 2.7 (v dd min) 5.5 (v dd max) v input voltages v adin v ss v dd v resolution b ad 88bits absolute accuracy a ad ? electrical specifications mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 194 freescale semiconductor 17.14 memory characteristics table 17-12. memory characteristics characteristic symbol min max unit ram data retention voltage v rdr 1.3 ? v flash program bus clock frequency ?1?mhz flash read bus clock frequency f r ead (1) 1. f read is defined as the frequency range for which the flash memory can be read. 32k 8m hz flash page erase time t e rase (2) 2. if the page erase time is longer than t erase (min), there is no erase-disturb, but it reduces the endurance of the flash memory. 4?ms flash mass erase time t me rase (3) 3. if the mass erase time is longer than t merase (min), there is no erase-disturb, bu t it reduces the endurance of the flash memory. 4?ms flash pgm / erase to hven set up time t nvs 10 ? mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 195 chapter 18 mechanical specifications 18.1 introduction this section gives the dimensions for: 20-pin plastic dual in-line package (case #738) 20-pin small outline integrated circuit package (case #751d) 28-pin plastic dual in-line package (case #710) 28-pin small outline integrated circuit package (case #751f) 32-pin shrink dual in-line package (case #1376) 32-pin low-profile quad flat pack (case #873a) 18.2 20-pin plastic dual in-line package (pdip) figure 18-1. 20-pin pdip (case #738) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimension b does not include mold flash. m l j 20 pl m b m 0.25 (0.010) t dim min max min max millimeters inches a 25.66 27.17 1.010 1.070 b 6.10 6.60 0.240 0.260 c 3.81 4.57 0.150 0.180 d 0.39 0.55 0.015 0.022 g 2.54 bsc 0.100 bsc j 0.21 0.38 0.008 0.015 k 2.80 3.55 0.110 0.140 l 7.62 bsc 0.300 bsc m 0 15 0 15 n 0.51 1.01 0.020 0.040 e 1.27 1.77 0.050 0.070 1 11 10 20 ?a? seating plane k n f g d 20 pl ?t? m a m 0.25 (0.010) t e b c f 1.27 bsc 0.050 bsc mechanical specifications mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 196 freescale semiconductor 18.3 20-pin small outline inte grated circuit package (soic) figure 18-2. 20-pin soic (case #751d) 18.4 28-pin plastic dual in-line package (pdip) figure 18-3. 28-pin pdip (case #710) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.150 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. ?a? ?b? 20 1 11 10 s a m 0.010 (0.25) b s t d 20x m b m 0.010 (0.25) p 10x j f g 18x k c ?t? seating plane m r x 45 dim min max min max inches millimeters a 12.65 12.95 0.499 0.510 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 notes: 1. positional tolerance of leads (d), shall be within 0.25 (0.010) at maximum material condition, in relation to seating plane and each other. 2. dimension l to center of leads when formed parallel. 3. dimension b does not include mold flash. 1 seating plane 15 14 28 m a b k c n f g d h j l dim min max min max inches millimeters a 36.45 37.21 1.435 1.465 b 13.72 14.22 0.540 0.560 c 3.94 5.08 0.155 0.200 d 0.36 0.56 0.014 0.022 f 1.02 1.52 0.040 0.060 g 2.54 bsc 0.100 bsc h 1.65 2.16 0.065 0.085 j 0.20 0.38 0.008 0.015 k 2.92 3.43 0.115 0.135 l 15.24 bsc 0.600 bsc m 0 28-pin small outline integrat ed circuit package (soic) mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 197 18.5 28-pin small outline inte grated circuit package (soic) figure 18-4. 28-pin soic (case #751f) 18.6 32-pin shrink dual in-line package (sdip) figure 18-5. 32-pin sdip (case #1376) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. j k f 1 15 14 28 -a- -b- 28x 14x d p s a m 0.010 (0.25) b s t m 0.010 (0.25) b m 26x g -t- seating plane c x 45 r m dim min max min max inches millimeters a 17.80 18.05 0.701 0.711 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.41 0.90 0.016 0.035 g 1.27 bsc 0.050 bsc j 0.23 0.32 0.009 0.013 k 0.13 0.29 0.005 0.011 m p 10.01 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 0 mechanical specifications mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 198 freescale semiconductor 18.7 32-pin low-profil e quad flat pack (lqfp) figure 18-6. 32-pin lqfp (case #873a) w k x 0.250 (0.010) gauge plane e c h detail ad notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ?ab? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums ?t?, ?u?, and ?z? to be determined at datum plane ?ab?. 5. dimensions s and v to be determined at seating plane ?ac?. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ?ab?. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.520 (0.020). 8. minimum solder plate thickness shall be 0.0076 (0.0003). 9. exact shape of each corner may vary from depiction. dim a min max min max inches 7.000 bsc 0.276 bsc millimeters b 7.000 bsc 0.276 bsc c 1.400 1.600 0.055 0.063 d 0.300 0.450 0.012 0.018 e 1.350 1.450 0.053 0.057 f 0.300 0.400 0.012 0.016 g 0.800 bsc 0.031 bsc h 0.050 0.150 0.002 0.006 j 0.090 0.200 0.004 0.008 k 0.500 0.700 0.020 0.028 m 12 ref 12 ref n 0.090 0.160 0.004 0.006 p 0.400 bsc 0.016 bsc q 1 5 1 5 r 0.150 0.250 0.006 0.010 v 9.000 bsc 0.354 bsc v1 4.500 bsc 0.177 bsc detail ad a1 b1 v1 4x s 4x b1 3.500 bsc 0.138 bsc a1 3.500 bsc 0.138 bsc s 9.000 bsc 0.354 bsc s1 4.500 bsc 0.177 bsc w 0.200 ref 0.008 ref x 1.000 ref 0.039 ref 9 ?t? ?z? ?u? t?u 0.20 (0.008) z ac t?u 0.20 (0.008) z ab 0.10 (0.004) ac ?ac? ?ab? m 8x ?t?, ?u?, ?z? t?u m 0.20 (0.008) z ac mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 199 chapter 19 ordering information 19.1 introduction this section contains ordering numbers for the mc68hc908jl8. 19.2 mc order numbers table 19-1. mc order numbers mc order number operating temperature range package mc68hc908jk8cp ?40 ordering information mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 200 freescale semiconductor mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 201 appendix a mc68hc08jl8 a.1 introduction this section introduces the mc68hc08jl8, the rom part equivalent to the mc68hc908jl8/jk8. the entire data book applies to this rom device, with exceptions outlined in this appendix. a.2 mcu block diagram figure a-1 shows the block diagram of the mc68hc08jl8. a.3 memory map the mc68hc08jl8 has 8,192 bytes of user rom from $dc00 to $fbff, and 36 bytes of user rom vectors from $ffdc to $ffff. on the mc68hc908jl8, these memory locations are flash memory. figure a-2 shows the memory map of the mc68hc08jl8. table a-1. summary of mc68hc08jl8 and mc68hc908jl8 differences mc68hc08jl8 mc68hc908jl8 memory ($dc00?$fbff) 8,192 bytes rom 8,192 bytes flash user vectors ($ffdc?$ffff) 36 bytes rom 36 bytes flash registers at $fe08 and $ffcf not used; locations are reserved. flash related registers. $fe08 ? flcr $ffcf ? flbpr mask option register ($ffd0) defined by mask; read only. read/write flash register. monitor rom ($fc00?$fdff and $fe10?$ffce) $fc00?$fdff: not used. $fe10?$ffce: used for testing purposes only. used for testing and flash programming/erasing. available packages 20-pin pdip (MC68HC08JK8) 20-pin soic (MC68HC08JK8) 28-pin pdip 28-pin soic 32-pin sdip 32-pin lqfp 20-pin pdip (mc68hc908jk8) 20-pin soic (mc68hc908jk8) 28-pin pdip 28-pin soic 32-pin sdip 32-pin lqfp mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 202 freescale semiconductor figure a-1. mc68hc08jl8 block diagram a.4 reserved registers the two registers at $fe08 and $ffcf ar e reserved locations on the mc68hc08jl8. on the mc68hc908jl8, these two locations are the flash control register and the flash block protect register respectively. system integration module arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 64 bytes external interrupt module internal bus * rst * irq power vss 2-channel timer interface module 1 keyboard interrupt module 8-bit analog-to-digital converter module vdd adc reference ddrb portb ptb7/adc7 ptb6/adc6 ptb5/adc5 ptb4/adc4 ptb3/adc3 ptb2/adc2 ptb1/adc1 ptb0/adc0 ddra porta pta6/kbi6** pta5/kbi5** ? pta4/kbi4** ? pta3/kbi3** ? pta2/kbi2** ? pta1/kbi1** ? pta0/kbi0** ? power-on reset module * pin contains integrated pull-up device. ** pin contains programmable pull-up device. ? led direct sink pin. osc1 osc2/rcclk crystal oscillator rc oscillator ddrd portd ptd7/rxd ** ?? ptd6/txd ** ?? ptd5/t1ch1 ptd4/t1ch0 ptd3/adc8 ? ptd2/adc9 ? ptd1/adc10 ptd0/adc11 break module computer operating properly module # pins available on 32-pin packages only. shared pin: osc2/rcclk/pta6/kbi6. pta7/kbi7** ? low-voltage inhibit module serial communications interface module pte ddre pte1/t2ch1 pte0/t2ch0 internal oscillator adc12/t2clk 2-channel timer interface module 2 user ram ? 256 bytes monitor rom ? 447 bytes # ## # ## # ## pins available on 28-pin and 32-pin packages only. ? 25ma open-drain if output pin. user rom ? 8,192 bytes user rom vectors ? 36 bytes shaded blocks indicate di fferences to mc68hc908jl8 mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 203 $0000 mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 204 freescale semiconductor a.5 mask option register the mask option register at $ffd0 is read only. the value is defined by mask option (hard-wired connections) specified at the ti me as the rom code submission. on the mc68hc908jl8, the mor is implemented as a flash, which can be programmed, erased, and read. a.6 monitor rom the monitor program (monitor rom: $fe10?$ffce) on the mc68hc08jl8 is for device testing only. $fc00?$fdff are unused. a.7 electrical specifications electrical specifications for the mc68hc908jl8 apply to the mc68hc08jl8, except for the parameters indicated below. a.7.1 dc electrical characteristics table a-2. dc electrical characteristics (5v) characteristic (1) 1. v dd = 4.5 to 5.5 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. symbol min typ (2) 2. typical values reflect average measurem ents at midpoint of voltage range, 25 mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 205 figure a-3. rc vs. frequency (5v @25 r ext c ext osc1 v dd mcu 0 01020304050 14 12 10 8 6 4 2 resistor, r ext (k ? r ext c ext osc1 v dd mcu 0 0 1020304050 14 12 10 8 6 4 2 resistor, r ext (k ? mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 206 freescale semiconductor a.9 mc68hc08jl8 order numbers these part numbers are generic numbers only. to pl ace an order, rom code must be submitted to the rom processing center (rpc). table a-5. mc68hc08jl8 order numbers mc order number operating temperature range package MC68HC08JK8cp ?40 mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 207 appendix b mc68hc908kl8 b.1 introduction this appendix introduces the mc68hc908kl8, an adc-less device of the mc68hc908jl8. the entire data book applies to this device, with exceptions outlined in this appendix. b.2 mcu block diagram figure b-1 shows the block diagram of the mc68hc908kl8. b.3 pin assignments figure b-2 and figure b-3 show the pin assignments for the mc68hc908kl8. table b-1. summary of mc68hc908kl8 and mc68hc908jl8 differences mc68hc908kl8 mc68hc908jl8 analog-to-digital converter (adc) ? 13-channel, 8-bit. registers at: $003c, $003e, and $003e not used; locations are reserved. adc registers. interrupt vector at: $ffde and $ffdf not used. adc interrupt vector. available packages ? ? 28-pin pdip 28-pin soic 32-pin sdip ? 20-pin pdip (mc68hc908jk8) 20-pin soic (mc68hc908jk8) 28-pin pdip 28-pin soic 32-pin sdip 32-pin lqfp mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 208 freescale semiconductor figure b-1. mc68hc908kl8 block diagram system integration module arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 64 bytes external interrupt module internal bus * rst * irq power vss 2-channel timer interface module 1 keyboard interrupt module vdd ddrb portb ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 ddra porta pta6/kbi6** pta5/kbi5** ? pta4/kbi4** ? pta3/kbi3** ? pta2/kbi2** ? pta1/kbi1** ? pta0/kbi0** ? power-on reset module * pin contains integrated pull-up device. ** pin contains programmable pull-up device. ? led direct sink pin. osc1 osc2/rcclk crystal oscillator rc oscillator ddrd portd ptd7/rxd ** ?? ptd6/txd ** ?? ptd5/t1ch1 ptd4/t1ch0 ptd3 ? ptd2 ? ptd1 ptd0 break module computer operating properly module # pins available on 32-pin packages only. shared pin: osc2/rcclk/pta6/kbi6. pta7/kbi7** ? low-voltage inhibit module serial communications interface module pte ddre pte1/t2ch1 pte0/t2ch0 internal oscillator t2clk 2-channel timer interface module 2 user flash ? 8,192 bytes user ram ? 256 bytes monitor rom ? 959 bytes user flash vectors ? 36 bytes # # # ? 25ma open-drain if output pin. mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 freescale semiconductor 209 figure b-2. 32-pin sdip pin assignment figure b-3. 28-pin pdip/soic pin assignment 1 2 3 4 5 6 7 32 31 30 29 28 27 26 25 24 23 22 12 13 14 21 20 19 8 9 10 11 t2clk pta7/kbi7 rst pta5/kbi5 ptd4/t1ch0 ptd5/t1ch1 ptd2 pta4/kbi4 ptd3 ptb0 ptb1 ptd1 ptb2 ptb3 irq pta0/kbi0 vss osc1 osc2/rcclk/pta6/kbi6 pta1/kbi1 vdd pta2/kbi2 pta3/kbi3 ptb7 ptb6 ptb5 ptd7/rxd ptd6/txd 15 16 18 17 ptd0 ptb4 pte0/t2ch0 pte1/t2ch1 1 2 3 4 5 6 7 28 27 26 25 24 23 22 21 20 19 18 12 13 14 17 16 15 8 9 10 11 rst pta5/kbi5 ptd4/t1ch0 ptd5/t1ch1 ptd2 pta4/kbi4 ptd3 ptb0 ptb1 ptd1 ptb2 ptb3 ptd0 ptb4 irq pta0/kbi0 vss osc1 osc2/rcclk/pta6/kbi6 pta1/kbi1 vdd pta2/kbi2 pta3/kbi3 ptb7 ptb6 ptb5 ptd7/rxd ptd6/txd pins not available on 28-pin packages pte0/t2ch0 pte1/t2ch1 t2clk pta7/kbi7 internal pads are unconnected. set these unused port i/os to output low. mc68hc908jl8/jk8 mc68hc08jl8/jk8 mc68hc908kl8 data sheet, rev. 3.1 210 freescale semiconductor b.4 reserved registers the following registers are reserved location on the mc68hc908kl8. b.5 reserved vectors the following are reserved interrupt vectors on the mc68hc908kl8. b.6 mc68hc908kl8 order numbers addr.register name bit 7654321bit 0 $003c reserved read: rrrrrrrr write: reset: $003d reserved read: rrrrrrrr write: reset: $003e reserved read: rrrrrrrr write: reset: figure b-4. reserved registers table b-2. reserved vectors vector priority int flag address vector ?if15 $ffde reserved $ffdf reserved table b-3. mc68hc908kl8 order numbers mc order number operating temperature range package mc68hc908kl8cp ?40 how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclai ms any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data shee ts and/or specificati ons can and do vary in different applications and actual perfo rmance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2005. all rights reserved. mc68hc908jl8 rev. 3.1, 3/2005 |
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